XA9572XL-15VQG44Q Xilinx Inc, XA9572XL-15VQG44Q Datasheet
XA9572XL-15VQG44Q
Specifications of XA9572XL-15VQG44Q
Available stocks
Related parts for XA9572XL-15VQG44Q
XA9572XL-15VQG44Q Summary of contents
Page 1
... Product Specification 0 XA9572XL Automotive CPLD Product Specification 0 0 Description The XA9572XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage automotive applications comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 15.5 ns. See overview. Maximum = +125° C Power Estimation ...
Page 2
... I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XA9572XL Architecture www.xilinx.com 54 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells Function 18 Block 3 Macrocells ...
Page 3
... OH = –500 μ 8 500 μ Max GND Max GND www.xilinx.com XA9572XL Automotive CPLD Value Units –0.5 to 4.0 –0.5 to 5.5 –0.5 to 5.5 –65 to +150 +125 by 4.0V. CCINT information on the Xilinx website. For Pb-free Min Max –40 +85 –40 +105 3.0 3.6 3.0 3.6 2.3 2 ...
Page 4
... XA9572XL Automotive CPLD Symbol Parameter I/O high-Z leakage current I/O capacitance IN Operating supply current I CC (low power mode, active) AC Characteristics Symbol T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO f Multiple FB internal operating frequency ...
Page 5
... RAI T Internal logic delay LOGI Feedback Delays T Fast CONNECT II feedback delay F Time Adders T Incremental product term allocator delay PTA T Slew-rate limited delay SLEW DS599 (v1.1) April 3, 2007 Product Specification Parameter www.xilinx.com XA9572XL Automotive CPLD XA9572XL-15 Min Max Units - 3.0 ...
Page 6
... XA9572XL Automotive CPLD XA9572XL I/O Pins Function Block Macrocell VQG44 VQG64 ( ( ( ( ( ( Notes: 1. Global control pin. 2. GTS1 6 BScan Function TQG100 Order Block - 16 213 210 207 204 201 198 195 192 3 (1) (1) 22 189 186 3 (1) (1) 23 183 180 177 3 (1) (1) 27 174 ...
Page 7
... R XA9572XL Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS V 3.3V CCINT V 2.5V/3.3V CCIO GND No Connects DS599 (v1.1) April 3, 2007 Product Specification VQG44 VQG64 15 26 17, 25 14, 21, 41 www.xilinx.com XA9572XL Automotive CPLD TQG100 22 23 ...
Page 8
... Package Speed Operating Range · Speed Device Ordering and (pin-to-pin Part Marking Number delay) XA9572XL-15VQG44I 15.5 ns XA9572XL-15VQG64I 15.5 ns XA9572XL-15TQG100I 15.5 ns XA9572XL-15VQG44Q 15.5 ns XA9572XL-15VQG64Q 15.5 ns XA9572XL-15TQG100Q 15.5 ns Notes: I-Grade –40° to +85°C; Q-Grade Device Speed Grade Package Type Pb -Free Number of Pins ...
Page 9
... Distribute SSOs (Simultaneously Switching Outputs) evenly around the CPLD to reduce switching noise. 10. Terminate high speed outputs to eliminate noise caused by very fast rising/falling edges. www.xilinx.com XA9572XL Automotive CPLD CCI ) before the V for the applications in CC CCIO 9 ...
Page 10
... XA9572XL Automotive CPLD Packaging Revision History The following table shows the revision history for this document. Date Version 01/12/07 1.0 Initial Xilinx release. 04/03/07 1.1 Add programming temperature range warning on page 1. 10 Revision www.xilinx.com R DS599 (v1.1) April 3, 2007 Product Specification ...