XA9572XL-15TQG100Q Xilinx Inc, XA9572XL-15TQG100Q Datasheet - Page 3

• Manufacturer Part Number: XA9572XL-15TQG100Q
• Description: IC CPLD 3.3V 72MCELL 100-TQFP
• Manufacturer: Xilinx Inc
• Series: XA9500XL XAr

Specifications of XA9572XL-15TQG100Q

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 15.5ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 72
• Number Of Gates: 1600
• Number Of I /o: 72
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Features: Automotive
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

Absolute Maximum Ratings
Recommended Operation Conditions
Quality and Reliability Characteristics
DC Characteristic Over Recommended Operating Conditions
DS599 (v1.1) April 3, 2007
Product Specification
Notes:
1.
2.
3.
4.
Symbol
Symbol
All automotive customers are required to set the Macrocell Power Setting to low, and set Logic Optimization to density.
Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. External I/O voltage may not exceed V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
For soldering guidelines and thermal considerations, see the
packages, see XAPP427.
V
Symbol
Symbol
V
V
I
I
V
V
OH
IH
T
OL
IL
T
N
V
CCINT
V
V
V
CCIO
V
V
ESD
STG
T
T
DR
PE
CC
TS
IN
IH
IL
A
O
J
R
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Input leakage current
I/O high-Z leakage current
Data Retention
Program/Erase Cycles (Endurance) @ T
Electrostatic Discharge (ESD)
Supply voltage relative to GND
Input voltage relative to GND
Voltage applied to 3-state output
Storage temperature (ambient)
Junction temperature
Ambient temperature
Supply voltage for internal logic and input buffers
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Low-level input voltage
High-level input voltage
Output voltage
Parameter
Parameter
(1,3)
Description
Parameter
(2)
(4)
(2)
www.xilinx.com
I
I
I
I
V
V
I-Grade
Q-Grade
OH
OH
OL
OL
CC
CC
= 8.0 mA
= 500 μA
= –500 μA
= –4.0 mA
A
= Max; V
= Max; V
Device Packaging
= 70°
Test Conditions
IN
IN
= GND or V
= GND or V
CCINT
information on the Xilinx website. For Pb-free
10,000
2,000
Min
20
by 4.0V.
CC
CC
–65 to +150
–0.5 to 4.0
–0.5 to 5.5
–0.5 to 5.5
Value
+125
Min
–40
3.0
2.0
90% V
–40
3.0
2.3
XA9572XL Automotive CPLD
0
0
Max
Min
2.4
-
-
-
-
-
-
-
CCIO
V
+105
Max
0.80
+85
3.6
3.6
2.7
5.5
CCIO
Max
±10
±10
0.4
0.4
-
-
Units
Cycles
Years
Units
Volts
o
o
V
V
V
C
C
Units
o
o
Units
V
V
V
V
V
V
C
C
μA
μA
V
V
V
V
3