XC95144XL-7TQG144I Xilinx Inc, XC95144XL-7TQG144I Datasheet
XC95144XL-7TQG144I
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XC95144XL-7TQG144I Summary of contents
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... C to +70° Description The XC95144XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems comprised of eight © 1998-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. ...
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... XC95144XL High Performance CPLD application note XAPP114, “Understanding XC9500XL CPLD Power.” 250 200 150 104 MHz 100 100 Clock Frequency (MHz) Figure 1: Typical I vs. Frequency for XC95144XL CC 2 178 MHz 150 200 www.xilinx.com R DS056 (v2.0) April 3, 2007 Product Specification ...
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... I/O/GSR 4 I/O/GTS Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. DS056 (v2.0) April 3, 2007 Product Specification JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC95144XL Architecture www.xilinx.com XC95144XL High Performance CPLD 54 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells ...
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... XC95144XL High Performance CPLD Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage relative to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Junction temperature J Notes: 1. Maximum DC undershoot below GND must be limited to either 0. mA, whichever is easier to achieve. During transitions, the device pins may undershoot to – ...
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... Output Type V CCIO 3.3V 2. Figure 3: AC Load Circuit www.xilinx.com XC95144XL High Performance CPLD Min Max - ±10 - ± (Typical) XC95144XL-7 XC95144XL-10 Min Max Min Max - 7.5 - 10.0 4 4.5 - 5.8 - 125.0 - 100 ...
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... XC95144XL High Performance CPLD Internal Timing Parameters Symbol Parameter Buffer Delays T Input buffer delay IN T GCK buffer delay GCK T GSR buffer delay GSR T GTS buffer delay GTS T Output buffer delay OUT T Output buffer enable/disable EN delay Product Term Control Delays T Product term clock delay ...
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... C3 375 4 (1) (1) A2 372 369 366 4 (1) ( 363 4 (1) ( 360 357 4 (1) ( 354 4 (1) ( 351 348 345 342 339 336 333 330 327 324 4 www.xilinx.com XC95144XL High Performance CPLD Macro- cell TQ100 TQ144 CS144 (1) (1) (1) ( (1) (1) (1) ( 118 ...
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... XC95144XL High Performance CPLD XC95144XL (Continued) Function Macro- Block cell TQ100 TQ144 CS144 – Notes: 1. The pin-outs are the same for Pb-free versions of packages. 8 BScan Function Order Block - - 213 210 207 204 201 198 7 66 M10 195 192 189 7 68 N11 ...
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... R XC95144XL Global, JTAG and Power Pins Pin Type TQ100 I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS V 3.3V 5, 57, 98 CCINT V 2.5V/3.3V 26, 38, 51, 88 CCIO GND 21, 31, 44, 62, 69, 75, 84, 100 No Connects Notes: 1. The pin-outs are the same for Pb-free versions of packages. ...
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... XC95144XL-10TQ144I 10 ns XC95144XL-10CS144I 10 ns XC95144XL-5TQG100C 5 ns XC95144XL-5TQG144C 5 ns XC95144XL-5CSG144C 5 ns XC95144XL-7TQG100C 7.5 ns XC95144XL-7TQG144C 7.5 ns XC95144XL-7CSG144C 7.5 ns XC95144XL-7TQG100I 7.5 ns XC95144XL-7TQG144I 7.5 ns XC95144XL-7CSG144I 7 XC95xxxXL TQ144 7C 1 Sample package with part marking. Pkg. No. of Symbol Pins TQ100 100-pin Thin Quad Flat Pack (TQFP) TQ144 ...
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... TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-free TQG144 144-pin Thin Quad Flat Pack (TQFP); Pb-free CSG144 144-ball Chip Scale Package (CSP); Pb-free = –40° to +85°C A Pb- Free Example: XC95144XL 144 C Device Speed Grade Package Type Pb -Free Number of Pins Temperature Range www ...
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... XC95144XL High Performance CPLD Revision History The following table shows the revision history for this document. Date Version 10/30/98 1.1 Minor corrections to CS144 pinout table. 11/13/98 1.2 V1.2 minor correction in CS144 pinout table. 06/20/02 1.3 Updated I Component Availability chart.Added additional I Characteristics table. ...