XCR3128XL-7TQ144C Xilinx Inc, XCR3128XL-7TQ144C Datasheet - Page 10

• Manufacturer Part Number: XCR3128XL-7TQ144C
• Description: IC CPLD 128MCELL 3.3V HP 144TQFP
• Manufacturer: Xilinx Inc
• Series: CoolRunner XPLA3r

Specifications of XCR3128XL-7TQ144C

• Programmable Type: In System Programmable (min 1K program/erase cycles)
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 128
• Number Of Gates: 3000
• Number Of I /o: 108
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Features: Low Power
• Voltage: 3.3V
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

XCR3128XL 128 Macrocell CPLD
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Additional Information
CoolRunner XPLA3 Data Sheets and Application Notes
Device Packages
Revision History
The following table shows the revision history for this document.
10
Notes:
1.
XCR3128XL-10VQ100I
XCR3128XL-10VQG100I
XCR3128XL-10CS144I
XCR3128XL-10CSG144I
XCR3128XL-10TQ144I
XCR3128XL-10TQG144I
04/07/00
05/03/00
12/08/00
01/17/01
04/19/01
08/10/01
01/08/02
01/27/03
11/20/00
04/11/01
Part Marking Number
Device Ordering and
Date
C = Commercial: T
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
A
= 0° to +70°C; I = Industrial: T
Initial Xilinx release.
Minor updates and added Boundary Scan to pinout table.
Updated pinout tables; corrected note in
Updated pinout tables.
Removed Timing Model.
Added Typical I/V curve,
Updated Typical I/V curve,
Moved
Updated T
AC Table, renamed T
T
closely resemble true test conditions, added note for T
Updated product availability and AC/DC parameters for -6 Commercial and -7 Industrial devices.
Updated T
updated system frequency to 175 MHz; removed Advance Information from -6 device; updated
Derating Curve for -6 device. Updated Ordering Information format.
CONFIG
(pin-to-pin
Speed
delay)
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
Figure 1
spec. Updated T
PCO
SUF
and T
(added T
and
VQG100
TQG144
CSG144
Symbol
VQ100
CS144
TQ144
Pkg.
FIN
Table 1
SU
PTCK
spec to match software timing. Added single p-term setup time (T
to T
A
Figure
HI
= –40° to +85°C
Figure
spec to correct a typo. Updated AC Load Circuit diagram to more
SU2
No. of
), T
to first page. Changed VQ144 to VQ100 in
www.xilinx.com
Pins
100
100
144
144
144
144
CONFIG
2; added
for setup time through the OR array. Added T
2: added voltage levels.
Very Thin Quad Flat Package (VQFP)
Very Thin Quad Flat Package (VQFP); Pb-Free
Chip Scale Package (CSP)
Chip Scale Package (CSP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
Device Package User Guide
, T
Table 4
INIT
Table
Revision
, T
F
2: Total User I/O; changed V
. Updated I
to read: "port enable pin is brought High".
Package Type
POD
CC
delay measurement.
vs. Frequency Curve for -6 device;
DS016 (v2.6) March 31, 2006
Table
OH
Product Specification
INIT
2.
spec.
spec. Updated
Operating
Range
SU1
I
I
I
I
I
I
) to
(1)
R