XC2C512-10FTG256C Xilinx Inc, XC2C512-10FTG256C Datasheet - Page 10

IC CR-II CPLD 512MCELL 256-FBGA

XC2C512-10FTG256C

Manufacturer Part Number
XC2C512-10FTG256C
Description
IC CR-II CPLD 512MCELL 256-FBGA
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Datasheets

Specifications of XC2C512-10FTG256C

Operating Temperature
0°C ~ 70°C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
9.2ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
12000
Number Of I /o
212
Mounting Type
Surface Mount
Package / Case
256-FTBGA
Features
Programmable
Voltage
1.8V
Memory Type
CMOS
No. Of Macrocells
512
No. Of I/o's
212
Propagation Delay
7.1ns
Global Clock Setup Time
2.6ns
Frequency
179MHz
Supply Voltage Range
1.7V To 1.9V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1407

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2C512-10FTG256C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC2C512-10FTG256C
Manufacturer:
XILINX
0
Part Number:
XC2C512-10FTG256C
0
CoolRunner-II CPLD Family
Design Security
Designs can be secured during programming to prevent
either accidental overwriting or pattern theft via readback.
Four independent levels of security are provided on-chip,
10
Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option
Figure 9: Macrocell Clock Chain with DualEDGE Option Shown
Synch Reset
CLK_CT
PTC
GCK2
CTC
PTC
GCK0
GCK1
GCK2
GCK0
GCK1
GCK2
www.xilinx.com
Clock
In
Synch Rst
eliminating any electrical or visual detection of configuration
patterns. These security bits can be reset only by erasing
the entire device. See
÷10
÷12
÷14
÷16
÷2
÷4
÷6
÷8
PTC
PTC
D/T
CE
CK
D/T
CE
CK
DS090_09_121201
FIF
Latch
DualEDGE
FIF
Latch
DualEDGE
WP170
Q
DS090 (v3.1) September 11, 2008
Q
for more detail.
Product Specification
R

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