XC2C512-10PQG208I Xilinx Inc, XC2C512-10PQG208I Datasheet - Page 23
![IC CR-II CPLD 512MCRCELL 208PQFP](/photos/6/71/67100/pq208_sml.jpg)
XC2C512-10PQG208I
Manufacturer Part Number
XC2C512-10PQG208I
Description
IC CR-II CPLD 512MCRCELL 208PQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Specifications of XC2C512-10PQG208I
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
9.2ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
12000
Number Of I /o
173
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Features
Programmable
Voltage
1.8V
Memory Type
CMOS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2C512-10PQG208I
Manufacturer:
Xilinx Inc
Quantity:
10 000
DS096 (v3.2) March 8, 2007
Product Specification
AA
AB
W
M
G
A
B
C
D
E
H
K
N
P
R
U
V
Y
F
T
L
J
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R
TMS
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
TDI
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Figure 8: FG324 Fine Pitch BGA
VCCIO4
VCCIO4
VCCIO3
VCCIO3
GND VCCIO4 VCCIO4 VCCIO2
GND VCCIO3 VCCIO3 VCCIO1
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FG324 Bottom View
www.xilinx.com
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO2
VCCIO1
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO2
VCCIO2
VCCIO1
VCCIO1
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XC2C512 CoolRunner-II CPLD
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
(4) - Clock Divide Reset
(5) - DataGATE Enable
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(5)
GND
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(2)
I/O(1)
VCC
I/O(2)
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(4)
I/O(3)
I/O
I/O
I/O
I/O
I/O
I/O
VAUX
I/O(1)
I/O(1)
I/O(1)
I/O(2)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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