XC2C512-7FGG324C Xilinx Inc, XC2C512-7FGG324C Datasheet - Page 10
![IC CR-II CPLD 512MCELL 324-FBGA](/photos/6/71/67103/xilinx-_324-fbga_sml.jpg)
XC2C512-7FGG324C
Manufacturer Part Number
XC2C512-7FGG324C
Description
IC CR-II CPLD 512MCELL 324-FBGA
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Specifications of XC2C512-7FGG324C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.1ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
32
Number Of Macrocells
512
Number Of Gates
12000
Number Of I /o
270
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
324-FBGA
Features
Programmable
Voltage
1.8V
Memory Type
CMOS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2C512-7FGG324C
Manufacturer:
INTEL
Quantity:
578
CoolRunner-II CPLD Family
Design Security
Designs can be secured during programming to prevent
either accidental overwriting or pattern theft via readback.
Four independent levels of security are provided on-chip,
10
Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option
Figure 9: Macrocell Clock Chain with DualEDGE Option Shown
Synch Reset
CLK_CT
PTC
GCK2
CTC
PTC
GCK0
GCK1
GCK2
GCK0
GCK1
GCK2
www.xilinx.com
Clock
In
Synch Rst
eliminating any electrical or visual detection of configuration
patterns. These security bits can be reset only by erasing
the entire device. See
÷10
÷12
÷14
÷16
÷2
÷4
÷6
÷8
PTC
PTC
D/T
CE
CK
D/T
CE
CK
✓
DS090_09_121201
✓
FIF
Latch
DualEDGE
FIF
Latch
DualEDGE
WP170
Q
DS090 (v3.1) September 11, 2008
Q
for more detail.
Product Specification
R