ATF750CL-15PC Atmel, ATF750CL-15PC Datasheet - Page 14
![IC CPLD 20MACROCELL LO-PWR 24DIP](/photos/6/70/67045/313-24-dip_sml.jpg)
ATF750CL-15PC
Manufacturer Part Number
ATF750CL-15PC
Description
IC CPLD 20MACROCELL LO-PWR 24DIP
Manufacturer
Atmel
Series
ATF750C(L)r
Datasheet
1.ATF750C-7JC.pdf
(25 pages)
Specifications of ATF750CL-15PC
Programmable Type
In System Programmable (min 1K program/erase cycles)
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Macrocells
10
Number Of I /o
10
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Features
Programmable
Voltage
5V
Memory Type
CMOS
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATF750CL-15PC
Manufacturer:
ATMEL
Quantity:
36
Part Number:
ATF750CL-15PC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
29. Preload of Registered Outputs
14
ATF750C(L)
The ATF750C(L)’s registers are provided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A V
ter high; a V
by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When the clock
term is pulsed high, the data on the I/O pins is placed into the register chosen by the select pin
.
Output Pin during Preload Cycle
Level Forced on Registered
IL
will force it low, independent of the output polarity. The PRELOAD state is entered
V
V
V
V
IH
IH
IL
IL
Select Pin
State
High
High
Low
Low
IH
Register #0 State
level on the I/O pin will force the regis-
after Cycle
High
Low
X
X
Register #1 State
after Cycle
0776L–PLD–11/08
High
Low
X
X