ATF1502AS-7AC44 Atmel, ATF1502AS-7AC44 Datasheet - Page 7
![IC CPLD 7NS 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATF1502AS-7AC44
Manufacturer Part Number
ATF1502AS-7AC44
Description
IC CPLD 7NS 44TQFP
Manufacturer
Atmel
Series
ATF1502AS(L)r
Datasheet
1.ATF1502ASL-25JU44.pdf
(26 pages)
Specifications of ATF1502AS-7AC44
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Macrocells
32
Number Of I /o
32
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Voltage
4.75 V ~ 5.25 V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
ATF1502AS7AC44
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Design
Software
Support
Power-up Reset
Security Fuse
Usage
Programming
0995K–PLD–6/05
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s
macrocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins,
with reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit
turned on), the reduced-power adder, t
include the data paths t
The ATF1502AS macrocell also has an option whereby the power can be reduced on a per-
macrocell basis. By enabling this power-down option, macrocells that are not used in an appli-
cation can be turned down, thereby reducing the overall power consumption of the device.
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching, and may be specified as fast switching in the design file.
ATF1502AS designs are supported by several third-party tools. Automated fitters allow logic
synthesis using a variety of high-level description languages and formats.
The ATF1502AS is designed with a power-up reset, a feature critical for state machine initial-
ization. At a point delayed slightly from V
the state of each output will depend on the polarity of its buffer. However, due to the asynchro-
nous nature of reset and uncertainty of how V
conditions are required:
1. The V
2. After reset occurs, all input and feedback setup times must be met before driving the
3. The clock must remain stable during T
The ATF1502AS has two options for the hysteresis about the reset level, V
Large. During the fitting process users may configure the device with the Power-up Reset hys-
teresis set to Large or Small. Atmel POF2JED users may select the Large option by including
the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be
properly reinitialized with the Large hysteresis option selected, the following condition is
added:
4. If V
When the Large hysteresis option is active, I
well.
A single fuse is provided to prevent unauthorized copying of the ATF1502AS fuse patterns.
Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains
accessible.
ATF1502AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG pro-
tocol. This capability eliminates package handling normally required for programming and
facilitates rapid design iterations and field changes.
clock pin high, and,
CC
CC
falls below 2.0V, it must shut off completely before the device is turned on again.
rise must be monotonic,
LAD
, t
LAC
, t
IC
, t
ACL
, t
CC
RPA
ACH
D
.
crossing V
, must be added to the AC parameters, which
CC
and t
CC
is reduced by several hundred microamps as
SEXP
actually rises in the system, the following
.
RST
, all registers will be initialized, and
ATF1502AS(L)
RST
, Small and
7