CY7C375I-125AC Cypress Semiconductor Corp, CY7C375I-125AC Datasheet - Page 8

• Manufacturer Part Number: CY7C375I-125AC
• Description: IC CPLD 128 MACROCELL 160LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultralogic™r

Specifications of CY7C375I-125AC

• Memory Type: CMOS
• Programmable Type: In-System Reprogrammable™ (ISR™) CMOS
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 128
• Number Of I /o: 128
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-LQFP
• Voltage: 5V
• Family Name: FLASH370i
• # Macrocells: 128
• Number Of Usable Gates: 3200
• Frequency (max): 158.3MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 128
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1472

Switching Characteristics
Document #: 38-03029 Rev. **
t
t
t
t
t
t
t
t
t
t
t
Ouptut Registered/Latched Mode Parameters
t
t
t
t
t
t
t
f
f
f
t
37x
Notes:
13. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
14. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C375i. This specification is met
Parameter
PD
PDL
PDLL
EA
ER
WL
WH
IS
IH
ICO
ICOL
CO
S
H
CO2
SCS
SL
HL
MAX1
MAX2
MAX3
OH
Combinatorial Mode Parameters
Input Registered/Latched Mode Parameters
–t
for the devices operating at the same ambient temperature and at the same power supply voltage.
IH
Input to Combinatorial Output
Input to Output Through Transparent Input
or Output Latch
Input to Output Through Transparent Input
and Output Latches
Input to Output Enable
Input to Output Disable
Clock or Latch Enable Input LOW Time
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to
Combinatorial Output
Input Register Clock or Latch Enable to
Output Through Transparent Output
Latch
Clock or Latch Enable to Output
Set-Up Time from Input to Clock or Latch
Enable
Register or Latch Data Hold Time
Output Clock or Latch Enable to Output
Delay (Through Memory Array)
Output Clock or Latch Enable to Output
Clock or Latch Enable (Through Memory
Array)
Set-Up Time from Input Through Transpar-
ent Latch to Output Register Clock or Latch
Enable
Hold Time for Input Through Transparent
Latch from Output Register Clock or Latch
Enable
Maximum Frequency with Internal Feed-
back (Least of 1/t
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(t
+ t
Maximum Frequency with External Feed-
back (Lesser of 1/(t
t
Output Data Stable from Output Clock
Minus Input Register Hold Time for
7C37x
WH
WH
,
[1]
), 1/(t
[9, 14]
S
+ t
Description
H
[1]
), or 1/t
SCS
Over the Operating Range
CO
[1]
, 1/(t
[1]
[1]
+ t
CO
S
S
+ t
)
) and 1/(t
H
[1]
), or 1/t
[1]
[1]
WL
CO
+
[9]
WL
[9]
)
[9]
158.3
7C375i–125
Min.
83.3
125
[13]
5.5
10
3
3
2
2
0
8
0
0
Max.
6.5
10
13
15
14
14
14
16
14
7C375i–100
Min.
76.9
100
143
10
12
3
3
2
2
6
0
0
0
Max.
12
15
16
16
16
16
18
16
7
7C374iL–83
Min.
62.5
125
7C375i–83
12
15
83
4
4
3
3
8
0
0
0
Max.
15
18
19
19
19
19
21
19
8
7C375iL–66
Min.
100
7C375i–66
10
15
20
66
50
5
5
4
4
0
0
0
CY7C375i
Max.
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20
22
24
24
24
24
26
10
24
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns