CY7C373I-100JC Cypress Semiconductor Corp, CY7C373I-100JC Datasheet - Page 3

• Manufacturer Part Number: CY7C373I-100JC
• Description: IC CPLD 64 MACROCELL 84-PLCC
• Manufacturer: Cypress Semiconductor Corp
• Series: Ultralogic™r

Specifications of CY7C373I-100JC

• Memory Type: FLASH
• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 12.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of I /o: 64
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Voltage: 3.3V/5V
• Family Name: FLASH370i
• # Macrocells: 64
• Number Of Usable Gates: 1600
• Propagation Delay Time: 12ns
• Number Of Logic Blocks/elements: 4
• # I/os (max): 64
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1269

Document #: 38-03030 Rev. *A
Functional Description
The 64 macrocells in the CY7C373i are divided between four
logic blocks. Each logic block includes 16 macrocells, a 72 x
86 product term array, and an intelligent product term allocator.
The logic blocks in the F
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Like all members of the F
in I/O resources. Every macrocell in the device features an
associated I/O pin, resulting in 64 I/O pins on the CY7C373i.
In addition, there is one dedicated input and four input/clock
pins.
Finally, the CY7C373i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used or the type of application, the timing param-
eters on the CY7C373i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
F
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Product Term Array
The product term array in the F
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in single
passes through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product term resources to macrocells that require
them. Any number of product terms between 0 and 16
inclusive can be assigned to any of the logic block macrocells
(this is called product term steering). Furthermore, product
terms can be shared among multiple macrocells. This means
that product terms that are common to more than one output
can be implemented in a single product term. Product term
steering and product term sharing help to increase the
effective density of the F
product term allocator is handled by software and is invisible
to the user.
I/O Macrocell
Each of the macrocells on the CY7C373i has a separate I/O
pin associated with it. In other words, each I/O pin is shared
by two macrocells. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed, polarity control over the input sum-term,
and two global clocks to trigger the register. The macrocell
also features a separate feedback path to the PIM so that the
register can be buried if the I/O pin is used as an input.
LASH
370i family. The CY7C373i includes four logic blocks.
LASH
LASH
LASH
370i architecture are connected
370i family, the CY7C373i is rich
LASH
370i CPLDs. Note that the
370i logic block includes
USE ULTRA37000
ALL NEW DESIGNS
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
four logic blocks on the CY7C373i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with F
PCI Compliance
The F
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
3.3V or 5.0V I/O operation
The F
3.3V and 5.0V systems. All devices have two sets of V
one set, V
another set, V
always be connected to a 5.0V power supply. However, the
V
supply, depending on the output requirements. When V
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When V
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is
available in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all F
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus
reducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to V
Design Tools
Development software for the CY7C371i is available from
Cypress’s Warp™, Warp Professional™, and Warp Enter-
prise™ software packages. Please refer to the data sheets on
these products for more details. Cypress also actively
supports almost all third-party design tools. Please refer to
third-party tool support for further information.
LASH
CCIO
LASH
370i ensures compliance with the PCI AC specifications
LASH
TM
pins may be connected to either a 3.3V or 5.0V power
FOR
CCINT
370i family of CMOS CPLDs are fully compliant with
370i family can be configured to operate in both
CCIO
, for internal operation and input buffers, and
, for I/O output drivers. V
LASH
CC
370i I/Os and dedicated input pins.
or GND.
CY7C373i
CCINT
CCIO
Page 3 of 12
LASH
pins must
pins are
LASH
370i.”
CC
pins:
CCIO
370i
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