CY37192VP160-100AC Cypress Semiconductor Corp, CY37192VP160-100AC Datasheet
CY37192VP160-100AC
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CY37192VP160-100AC Summary of contents
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... BGA, and Fine-Pitch BGA packages — Lead (Pb)-free packages available Note: 1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V Cypress Semiconductor Corporation Document #: 38-03007 Rev. *E 5V, 3.3V, ISR™ High-Performance CPLDs General Description The Ultra37000™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance ...
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Selection Guide 5.0V Selection Guide General Information Device Macrocells CY37032 32 CY37064 64 CY37128 128 CY37192 192 CY37256 256 CY37384 384 CY37512 512 Speed Bins Device 200 167 CY37032 X CY37064 X CY37128 X CY37192 CY37256 CY37384 CY37512 Device-Package Offering ...
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Speed Bins Device 200 167 CY37032V CY37064V CY37128V CY37192V CY37256V CY37384V CY37512V Device-Package Offering and I/O Count Device CY37032V 37 37 CY37064V CY37128V CY37192V CY37256V CY37384V CY37512V Architecture Overview of Ultra37000 Family Programmable Interconnect Matrix The PIM ...
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FROM PIM PRODUCT TERM ARRAY TO PIM Figure 1. Logic Block with 50% Buried Macrocells Low-Power Option Each logic block can operate in high-speed mode for critical path performance low-power mode for power conser- ...
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The buried macrocell also supports input register capability. The buried macrocell can be configured to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried ...
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FROM CLOCK 1 POLARITY MUXES 2 3 C10 INPUT/CLOCK PIN D 0 FROM CLOCK 1 O POLARITY INPUT 2 CLOCK PINS Clocking Each I/O and buried macrocell has access to four synchronous clocks (CLK0, ...
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COMBINATORIAL SIGNAL INPUT REGISTERED SIGNAL D,T,L O INPUT CLOCK Figure 5. Timing Model for CY37128 JTAG and PCI Standards PCI Compliance 5V operation of the Ultra37000 is fully ...
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The third programming option for Ultra37000 devices is to utilize the embedded controller or processor that already exists in the system. The Ultra37000 ISR software assists in this method by converting the device JEDEC maps into the ISR serial stream ...
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Logic Block Diagrams CY37032/CY37032V 16 I/Os −I/O I CY37064/CY37064V 16 I/Os I/O -I I/Os I/O -I TDI JTAG Tap TCK TDO Controller TMS Document #: 38-03007 Rev. *E Clock/ Input Input 4 1 ...
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Logic Block Diagrams (continued) CY37128/CY37128V 16 I/Os I/O –I I/Os I/O –I I/Os I/O –I I/Os I/O –I CY37192/CY37192V 10 I/Os I/O –I I/Os I/O –I/O ...
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Logic Block Diagrams (continued) CY37256/CY37256V 12 I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I/O 60 ...
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Logic Block Diagrams (continued) CY37384/CY37384V 12 I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I/O 60 ...
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Logic Block Diagrams (continued) CY37512/CY37512V 12 I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I/O 60 ...
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Device Characteristics Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V ...
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Inductance Parameter Description Test Conditions L Maximum Pin V = 5.0V IN Inductance MHz Capacitance [5] Parameter Description C Input/Output Capacitance I/O C Clock Signal Capacitance CLK C Dual-Function Pins DP Endurance Characteristics [5] Parameter ...
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Inductance Parameter Description Test Conditions L Maximum Pin V = 3.3V IN Inductance MHz Capacitance [5] Parameter Description C Input/Output Capacitance I/O C Clock Signal Capacitance CLK C Dual Functional Pins DP Endurance Characteristics [5] ...
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Parameter t 1.5V ER(–) t 2.6V ER(+) t 1.5V EA(+) t V EA(–) Switching Characteristics Over the Operating Range Parameter Combinatorial Mode Parameters [13, 14, 15] t Input to Combinatorial Output PD [13, 14, 15] t Input to Output ...
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Switching Characteristics Over the Operating Range (continued) Parameter Product Term Clocking Parameters [13, 14, 15] t Product Term Clock or Latch Enable (PTCLK) to Output COPT t Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) SPT ...
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Switching Characteristics Over the Operating Range 200 MHz 167 MHz 154 MHz Parameter Combinatorial Mode Parameters [13, 14, 15 6.5 PD [13, 14, 15 12.5 PDL [13, 14, 15 13.5 PDLL [13, 14, 15] ...
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Switching Characteristics Over the Operating Range (continued) 200 MHz 167 MHz 154 MHz Parameter [13, 14, 15 [13 [13, 14, 15 User Option Parameters ...
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Switching Waveforms (continued) Registered Output with Product Term Clocking Input Going Through the Array INPUT PRODUCT TERM CLOCK REGISTERED OUTPUT Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register INPUT PRODUCT TERM CLOCK REGISTERED OUTPUT Latched Output ...
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Switching Waveforms (continued) Registered Input REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK Clock to Clock INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Document #: 38-03007 Rev ...
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Switching Waveforms (continued) Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS Document #: 38-03007 Rev. *E ...
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Power Consumption Typical 5.0V Power Consumption CY37032 The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. CY37064 9 0 ...
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Typical 5.0V Power Consumption (continued) CY37128 The typical pattern is a 16-bit up counter, per logic ...
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Typical 5.0V Power Consumption (continued) CY37256 The typical pattern is a 16-bit up counter, per logic block, with outputs ...
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Typical 5.0V Power Consumption (continued) CY37512 The typical pattern is a 16-bit up counter, per logic block, with ...
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Typical 3.3V Power Consumption (continued) CY37064V The typical pattern is a 16-bit up counter, per logic block, with outputs ...
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Typical 3.3V Power Consumption (continued) CY37192V The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. CY37256V 1 ...
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Typical 3.3V Power Consumption (continued) CY37384V The typical pattern is ...
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Pin Configurations I/O /TCK 5 I/O I/O CLK 2 JTAG GND CLK 0 I/O I/O I/O I/O I/O 5 CLK JTAG CLK I/O Document #: 38-03007 Rev. *E 44-pin TQFP (A44) Top View ...
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Pin Configurations (continued Note: 20. For 3.3V versions (Ultra37000V CCO I I /TCK I I/O 11 I/O 16 ...
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Pin Configurations (continued) 100 TCK 1 GND CLK / ...
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Pin Configurations (continued) 100-ball Fine-Pitch BGA (BB100) for CY37064V I/O 24 100-ball ...
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Pin Configurations (continued) GND I I/O /TCK GND I I I/O ...
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Pin Configurations (continued) GND I I TCK GND ...
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Pin Configurations (continued) GND I TCK 8 I I/O 29 GND 13 ...
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Pin Configurations (continued GND I/O NC I/O I/O I I/O I/O I/O I/O I/O I I/O NC I/O ...
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Pin Configurations (continued GND GND I/O I GND I/O I/O I I/O I I/O I/O I ...
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Pin Configurations (continued GND GND I/O I/O I/O I/O I/O I GND NC I/O I/O I/O I/O I/O I ...
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Pin Configurations (continued) A GND GND NC I/O I/O I GND GND GND NC I/O I GND GND GND I/O I I/O NC GND I/O I/O I/O 44 ...
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Ordering Information Cypress Semiconductor ID Family Type 37 = Ultra37000 Family Macrocell Density Macrocells 256 = 256 Macrocells ...
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Ordering Information (continued) Speed Macrocells (MHz) Ordering Code 64 154 CY37064P44-154AC CY37064P44-154JC CY37064P84-154JC CY37064P100-154AC CY37064P44-154AI CY37064P44-154AXI CY37064P44-154JI CY37064P44-154JXI CY37064P84-154JI CY37064P100-154AI 5962-9951902QYA 125 CY37064P44-125AC CY37064P44-125AXC CY37064P44-125JC CY37064P44-125JXC CY37064P84-125JC CY37064P100-125AC CY37064P100-125AXC CY37064P44-125AI CY37064P44-125AXI CY37064P44-125JI CY37064P84-125JI CY37064P100-125AI CY37064P100-125AXI 5962-9951901QYA Document #: 38-03007 ...
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Ordering Information (continued) Speed Macrocells (MHz) Ordering Code 128 167 CY37128P84-167JC CY37128P84-167JXC CY37128P100-167AC CY37128P100-167AXC CY37128P160-167AC CY37128P160-167AXC 125 CY37128P84-125JC CY37128P84-125JXC CY37128P100-125AC CY37128P100-125AXC CY37128P160-125AC CY37128P160-125AXC CY37128P84-125JI CY37128P84-125JXI CY37128P100-125AI CY37128P100-125AXI CY37128P160-125AI CY37128P160-125AXI 5962-9952102QYA 100 CY37128P84-100JC CY37128P84-100JXC CY37128P100-100AC CY37128P100-100AXC CY37128P160-100AC CY37128P160-100AXC CY37128P84-100JI CY37128P100-100AI ...
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Ordering Information (continued) Speed Macrocells (MHz) Ordering Code 256 154 CY37256P160-154AC CY37256P160-154AXC CY37256P208-154NC CY37256P256-154BGC 125 CY37256P160-125AC CY37256P160-125AXC CY37256P208-125NC CY37256P256-125BGC CY37256P160-125AI CY37256P160-125AXI CY37256P208-125NI CY37256P256-125BGI 5962-9952302QZC 83 CY37256P160-83AC CY37256P160-83AXC CY37256P208-83NC CY37256P256-83BGC CY37256P160-83AI CY37256P160-83AXI CY37256P208-83NI CY37256P256-83BGI 5962-9952301QZC 384 125 CY37384P208-125NC CY37384P256-125BGC 83 ...
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Ordering Information (continued) Speed Macrocells (MHz) Ordering Code 512 125 CY37512P208-125NC CY37512P256-125BGC CY37512P352-125BGC 100 CY37512P208-100NC CY37512P256-100BGC CY37512P352-100BGC CY37512P208-100NI CY37512P256-100BGI CY37512P352-100BGI 5962-9952502QZC 83 CY37512P208-83NC CY37512P256-83BGC CY37512P352-83BGC CY37512P208-83NI CY37512P256-83BGI CY37512P352-83BGI 5962-9952501QZC 3.3V Ordering Information Speed Macrocells (MHz) Ordering Code 32 143 ...
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... CY37128VP160-125AXI 83 CY37128VP100-83AC CY37128VP100-83AXC CY37128VP100-83BBC CY37128VP160-83AC CY37128VP160-83AXC CY37128VP100-83AI CY37128VP100-83AXI CY37128VP100-83BBI CY37128VP160-83AI CY37128VP160-83AXI 5962-9952201QYA 192 100 CY37192VP160-100AC CY37192VP160-100AXC 66 CY37192VP160-66AC CY37192VP160-66AXC CY37192VP160-66AI Document #: 38-03007 Rev. *E Ultra37000 CPLD Family Package Name Package Type A44 44-Lead Thin Quad Flatpack A44 44-Lead Lead Free Thin Quad Flatpack ...
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Ordering Information (continued) Speed Macrocells (MHz) Ordering Code 256 100 CY37256VP160-100AC CY37256VP160-100AXC CY37256VP208-100NC CY37256VP256-100BGC CY37256VP256-100BBC CY37256VP160-100AI CY37256VP160-100AXI 66 CY37256VP160-66AC CY37256VP160-66AXC CY37256VP208-66NC CY37256VP256-66BGC CY37256VP256-66BBC CY37256VP160-66AI CY37256VP256-66BGI CY37256VP256-66BBI 5962-9952401QZC 384 83 CY37384VP208-83NC CY37384VP256-83BGC 66 CY37384VP208-66NC CY37384VP256-66BGC CY37384VP208-66NI CY37384VP256-66BGI 512 83 CY37512VP208-83NC ...
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Package Diagrams 44-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack A44 44-Lead Lead (Pb)-Free Plastic Leaded Chip Carrier J67 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85064-*B 51-85003-*A Page ...
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Package Diagrams (continued) Document #: 38-03007 Rev. *E 44-Lead Ceramic Leaded Chip Carrier Y67 Ultra37000 CPLD Family 51-80014-** Page ...
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Package Diagrams (continued) 48-Ball (7 7 1.2 mm, 0.80 pitch) Thin BGA BA48D 84-Lead Lead (Pb)-Free Plastic Leaded Chip Carrier J83 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85109-*C 51-85006-*A Page ...
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Package Diagrams (continued) Document #: 38-03007 Rev. *E 84-Lead Ceramic Leaded Chip Carrier Y84 Ultra37000 CPLD Family 51-80095-*A Page ...
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Package Diagrams (continued) 100-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85048-*B Page ...
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Package Diagrams (continued) 100-Ball Thin Ball Grid Array ( 1.4 mm) BB100 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85107-*B Page ...
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Package Diagrams (continued) 160-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack ( 1.4 mm) (TQFP) A160 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85049-*B Page ...
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Package Diagrams (continued) 160-Lead Ceramic Quad Flatpack (Cavity Up) U162 PIN 1 SEATING PLANE 2.03(.080) 2.79(.110) 0.050(.002) 0.500(.020) Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 25.35±0.10 (.998±.004) TYP. 0.650(.0256) TYP. 0.300(.012) TYP. 28.00 ±0.10 (1.102 ±.004) SQ. 31.20 ±0.25 ...
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Package Diagrams (continued) Document #: 38-03007 Rev. *E 208-Lead Plastic Quad Flatpack N208 Ultra37000 CPLD Family 51-85069-*B Page ...
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Package Diagrams (continued) 208-Lead Ceramic Quad Flatpack (Cavity Up) U208 PIN 1 3.43(.135) 3.94(.155) SEATING PLANE 0.050(.002) 0.500(.020) Document #: 38-03007 Rev. *E 0.50(.0197) TYP. 0.20(.008) TYP. 28.00 ±0.10 (1.102 ±.008) SQ. 31.22 ±0.25 (1.229 ±.010) SQ. SEE DETAIL A ...
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Package Diagrams (continued) TOP VIEW PIN 1 CORNER SEATING PLANE ...
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Package Diagrams (continued) 292-Ball Plastic Ball Grid Array PBGA ( 2.33 mm) BG292 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85097-*B Page ...
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Package Diagrams (continued) 388-Ball Plastic Ball Grid Array PBGA ( 2.33 mm) BG388 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85103-*C Page ...
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... Document #: 38-03007 Rev. *E © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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Addendum 3.3V Operating Range (CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143B Range Ambient Temperature Commercial Document #: 38-03007 Rev. *E Ultra37000 CPLD Family [2] Junction Temperature 0°C to +70°C 0°C to +90°C AC 3.3V ± 0.16V Page ...
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... CY37192P160-83AXI, CY37256P160-154AXC, CY37256P160-125AXC, CY37256P160-125AXI, CY37256P160-83AXC, CY37256P160-83AXI, CY37032VP44-143AXC, CY37032VP44-100AXC, CY37032VP44-100AXI, CY37032VP44-100JXI, CY37064VP44-143AXC, CY37064VP100-143AXC, CY37064VP44-100AXC, CY37064VP100-100AXC, CY37064VP44-100AXI, CY37064VP100-100AXI, CY37128VP100-125AXC, CY37128VP160-125AXC, CY37128VP160-125AXI, CY37128VP100-83AXC, CY37128VP160-83AXC, CY37128VP100-83AXI, CY37128VP160-83AXI, CY37192VP160-100AXC, CY37192VP160-66AXC, CY37256VP160-100AXC, CY37256VP160-100AXI, CY37256VP160-66AXC Added Package Diagram BG292 Updated all PBGA package type information (BG292 & BG388) Page ...