CY39200V208-125NTXC Cypress Semiconductor Corp, CY39200V208-125NTXC Datasheet - Page 19

• Manufacturer Part Number: CY39200V208-125NTXC
• Description: IC CPLD 200K GATE 208BQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V208-125NTXC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 136
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Voltage: 2.5V, 3.3V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: CY39200V208125NTX

Switching Characteristics — Parameter Descriptions
Note:
Document #: 38-03039 Rev. *D
13. PLL is offered with Delta39K 3.3/2.5V versions only
Product Term Clock
t
t
t
t
t
t
Miscellaneous Delays
t
t
t
t
t
t
PLL Parameters
t
t
t
t
t
f
f
f
P
f
JTAG Parameters
t
t
t
t
t
t
t
t
MCSPT
MCHPT
MCCOPT
SCS2PT
CHSW
CL2CL
CPLD
MCCD
IOD
IOIN
CKIN
IOREGPIN
MCCJ
DWSA
DWOSA
LOCK
INDUTY
PLLI
PLLO
PLLVCO
MPLLI
JCKH
JCKL
JCP
JSU
JH
JCO
JXZ
JZX
Channel Interconnect Parameters
SAPLLI
Parameter
[13]
Set-up time for macrocell used as input register, from input to product term clock
Hold time of macrocell used as an input register
Product term clock to output delay from input pin
Register to register delay through array logic in different clusters on the same channel using a product term
clock
Adder for a signal to switch from a horizontal to vertical channel and vice-versa
Cluster-to-cluster delay adder (through channels and channel PIM)
Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This
parameter can be added to the t
required by a given signal path
Adder for carry chain logic per macrocell
Delay from the input of the output buffer to the I/O pin
Delay from the I/O pin to the input of the channel buffer
Delay from the clock pin to the input of the clock driver
Delay from the I/O pin to the input of the I/O register
Maximum cycle to cycle jitter time
PLL zero phase delay with clock tree deskewed
PLL zero phase delay without clock tree deskewed
Lock time for the PLL
Input duty cycle
Input frequency of the PLL
Output frequency of the PLL
PLL VCO frequency of operation
Percentage modulation allowed (spread awareness) on the PLL input clock
Frequency of modulation allowed on PLL input clock. This specifies how fast the f
f
TCLK HIGH time
TCLK LOW time
TCLK clock period
JTAG port set-up time (TDI/TMS inputs)
JTAG port hold time (TDI/TMS inputs)
JTAG port clock to output time (TDO)
JTAG port valid output to high impedance (TDO)
JTAG port high impedance to valid output (TDO)
PLLI
* (1- P
SAPLLI
PRELIMINARY
/100) and f
PLLI
* (1+ P
PD
and t
SAPLLI
SCS
/100)
parameters for each extra pass through the AND/OR array
Description
Over the Operating Range
Delta39K™ ISR™
[12]
(continued)
CPLD Family
PLLI
sweeps between
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