CY37064P84-154JXI Cypress Semiconductor Corp, CY37064P84-154JXI Datasheet - Page 29
![IC CPLD 64 MACROCELL 84-PLCC](/photos/40/85/408595/plcc-84_sml.jpg)
CY37064P84-154JXI
Manufacturer Part Number
CY37064P84-154JXI
Description
IC CPLD 64 MACROCELL 84-PLCC
Manufacturer
Cypress Semiconductor Corp
Series
Ultra37000™r
Datasheet
1.CY37064P44-125JXC.pdf
(64 pages)
Specifications of CY37064P84-154JXI
Programmable Type
In-System Reprogrammable™ (ISR™) CMOS
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Macrocells
64
Number Of I /o
69
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
84-PLCC
Voltage
5V
Memory Type
CMOS
Family Name
Ultra 37000
# Macrocells
64
Number Of Usable Gates
2000
Frequency (max)
154MHz
Propagation Delay Time
7.5ns
Number Of Logic Blocks/elements
4
# I/os (max)
69
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
84
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY37064P84-154JXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY37064P84-154JXIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-03007 Rev. *E
Typical 3.3V Power Consumption (continued)
CY37192V
CY37256V
1 2 0
1 0 0
1 4 0
1 2 0
1 0 0
8 0
6 0
4 0
2 0
0
8 0
6 0
4 0
2 0
0
0
0
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
2 0
2 0
V
V
CC
CC
4 0
4 0
= 3.3V, T
= 3.3V, T
F r e q u e n c y ( M H z )
A
A
F r e q u e n c y ( M H z )
= Room Temperature
= Room Temperature
6 0
6 0
L o w P o w e r
L o w P o w e r
8 0
8 0
Ultra37000 CPLD Family
1 0 0
1 0 0
H ig h S p e e d
H ig h S p e e d
1 2 0
1 2 0
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