CY39200V208-83NTXC Cypress Semiconductor Corp, CY39200V208-83NTXC Datasheet - Page 10

• Manufacturer Part Number: CY39200V208-83NTXC
• Description: IC CPLD 200K GATE 208BQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V208-83NTXC

• Programmable Type: In-System Reprogrammable™ (ISR™) CMOS
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 136
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Voltage: 2.5V
• Memory Type: SRAM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -

register that can be configured as an input or output register.
The output buffer has a slew rate control option that can be
used to configure the output for a slower slew rate. The input
of the device and the pin output can each be configured as
registered or combinatorial; however, only one path can be
configured as registered in a given design.
The output enable in an I/O cell can be selected from one of
the four global control signals or from one of two Output
Control Channel (OCC) signals. The output enable can be
configured as always enabled or always disabled or it can be
controlled by one of the remaining inputs to the mux. The
selection is done via a mux that includes V
inputs.
I/O Signals
There are four dedicated inputs (GCTL[3:0]) that are used as
Global I/O Control Signals available to every I/O cell. These
global I/O control signals may be used as output enables,
register resets and register clock enables as shown in Figure
8. These global control signals, driven from four dedicated
pins, can only be used as active-high signals and are available
only to the I/O cells thereby implementing fast resets, register
and output enables.
Document #: 38-03039 Rev. *D
Output PIM
To Routing
Channel
From
PRELIMINARY
CC
Figure 8. Block Diagram of I/O Cell
and GND as
Input
Mux
2
3
3
C
C
C
C
Clock Mux
Register Reset
Mux
Register Enable
Mux
Polarity
Clock
Mux
C
C
Register Input
Mux
In addition, there are six OCC signals available to each I/O
cell. These control signals may be used as output enables,
register resets and register clock enables as shown in Figure
8. Unlike global control signals, these OCC signal can be
driven from internal logic or and I/O pin.
One of the four global clocks can be selected as the clock for
the I/O cell register. The clock mux output is an input to a clock
polarity mux that allows the input/output register to be clocked
on either edge of the clock
OE Mux
3
C
D
E
RES
Q
Figure 7. Delta39K I/O Bank Block Diagram
Output Mux
D
C
RES
Q
bank 7
bank 2
Control
Registered OE
Slew
Rate
C
Mux
C
Delta39K
Delta39K
Hold
Bus
C
Delta39K™ ISR™
I/O
bank 6
bank 3
CPLD Family
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