CY37256VP256-66BBI Cypress Semiconductor Corp, CY37256VP256-66BBI Datasheet - Page 16
![no-image](/images/manufacturer_photos/0/1/179/cypress_semiconductor_corp_sml.jpg)
CY37256VP256-66BBI
Manufacturer Part Number
CY37256VP256-66BBI
Description
IC CPLD 256 MACROCELL 256LFBGA
Manufacturer
Cypress Semiconductor Corp
Series
Ultra37000™r
Specifications of CY37256VP256-66BBI
Programmable Type
In-System Reprogrammable™ (ISR™) CMOS
Delay Time Tpd(1) Max
20.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Macrocells
256
Number Of I /o
197
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-LFBGA
Voltage
3.3V
Memory Type
CMOS
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY37256VP256-66BBI
Manufacturer:
CY
Quantity:
39
Company:
Part Number:
CY37256VP256-66BBI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Characteristics
Document Number : 38-03007 Rev. *G
Combinatorial Mode Parameters
t
t
t
t
t
Input Register Parameters
t
t
t
t
t
t
Synchronous Clocking Parameters
t
t
t
t
t
t
t
PD
PDL
PDLL
EA
ER
WL
WH
IS
IH
ICO
ICOL
CO
S
H
CO2
SCS
SL
HL
[13]
[13]
[13, 14, 15]
[13, 14, 15]
[11, 13]
[14, 15]
[13, 14, 15]
[13, 14, 15]
[13, 14, 15]
[13]
Parameter
[13, 14, 15]
[13, 14, 15]
Parameter
t
t
t
t
ER(–)
ER(+)
EA(+)
EA(–)
[11]
Input to Combinatorial Output
Input to Output Through Transparent Input or Output Latch
Input to Output Through Transparent Input and Output Latches
Input to Output Enable
Input to Output Disable
Clock or Latch Enable Input LOW Time
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to Combinatorial Output
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
Synchronous Clock (CLK
Set-Up Time from Input to Sync. Clk (CLK
Register or Latch Data Hold Time
Output Synchronous Clock (CLK
Delay (Through Logic Array)
Output Synchronous Clock (CLK
Clock (CLK
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK
CLK
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK
CLK
1
1
, CLK
, CLK
2
2
0
, or CLK
, or CLK
, CLK
Over the Operating Range
1.5V
2.6V
1.5V
V
1
V
, CLK
the
X
3
3
) or Latch Enable
) or Latch Enable
2
0
, or CLK
, CLK
(d) Test Waveforms
1
0
0
, CLK
, CLK
, CLK
3
) or Latch Enable (Through Logic Array)
V
V
V
V
2
[8]
1
1
OH
OL
X
, or CLK
[8]
, CLK
X
, CLK
0
Description
0.5V
0.5V
0.5V
[12]
, CLK
0.5V
2
2
, or CLK
, or CLK
3
1
) or Latch Enable to Output
Output Waveform—Measurement Level
, CLK
3
3
2
) or Latch Enable to Combinatorial Output
) or Latch Enable to Output Synchronous
, or CLK
3
) or Latch Enable
Ultra37000 CPLD Family
V
V
V
V
OL
X
X
OH
0
Page 16 of 43
,
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback