XC95288-15HQ208I Xilinx Inc, XC95288-15HQ208I Datasheet
XC95288-15HQ208I
Specifications of XC95288-15HQ208I
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XC95288-15HQ208I Summary of contents
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... XC9500 devices Table 2. The XC9500 fam- XC95216 XC95288 216 288 4,800 6,400 216 288 7 4.5 6.0 8.0 4.5 6.0 8.0 111.1 92.2 66.7 56 ...
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... See XCN07010 for details. provides programmable logic capability with 36 inputs and 18 outputs. The Fast CONNECT switch matrix connects all FB outputs and input signals to the FB inputs. For each FB outputs (depending on package pin-count) and www.xilinx.com XC95216 XC95288 - - - - - - - - - - - ...
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R associated output enable signals drive directly to the IOBs. See Figure 1. 3 JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS Note: Function block outputs (indicated by the bold ...
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XC9500 In-System Programmable CPLD Family From 36 Fast CONNECT II Switch Matrix 4 Macrocell 1 Product Programmable Term AND-Array Allocators Macrocell 18 1 Global Set/Reset Figure 2: XC9500 Function Block www.xilinx.com 18 To Fast CONNECT II Switch Matrix 18 OUT ...
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R Macrocell Each XC9500 macrocell may be individually configured for a combinatorial or registered function. The macrocell and associated FB logic is shown in Figure Five direct product terms from the AND-array are available for use as primary data inputs ...
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XC9500 In-System Programmable CPLD Family All global control signals are available to each individual macrocell, including clock, set/reset, and output enable sig- nals. As shown in Figure 4, the macrocell register clock originates from either of three global clocks or ...
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R Product Term Allocator The product term allocator controls how the five direct prod- uct terms are assigned to each macrocell. For example, all five direct terms can drive the OR function as shown in Figure 5. Product Term Allocator ...
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XC9500 In-System Programmable CPLD Family The product term allocator can re-assign product terms from any macrocell within the FB by combining partial sums of products over several macrocells, as shown in In this example, the incremental delay is only 2 ...
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R The internal logic of the product term allocator is shown in Figure 8. From Upper Macrocell From Lower Macrocell DS063 (v5.5) June 25, 2007 Product Specification XC9500 In-System Programmable CPLD Family To Upper Macrocell Product Term Allocator To Lower ...
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XC9500 In-System Programmable CPLD Family Fast CONNECT Switch Matrix The Fast CONNECT switch matrix connects signals to the FB inputs, as shown in Figure 9. All IOB outputs (corre- sponding to user pin inputs) and all FB outputs drive the ...
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... To other Macrocells OUT PTOE Global OE 1 Global OE 2 Global OE 3 Global OE 4 www.xilinx.com ) to ensure that the input thresh- CCINT CCIO I/O Block V CCIO Pull-up Resistor* 1 User- Programmable Ground 0 Slew Rate Control Available in XC95216 and XC95288 DS063_10_092203 voltage. I/O 11 ...
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XC9500 In-System Programmable CPLD Family Each output has independent slew rate control. Output edge rates may be slowed down to reduce system noise (with an additional time delay of T SLEW ming. See Figure 11. Each IOB provides user programmable ...
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R In-System Programming XC9500 devices are programmed in-system via a standard 4-pin JTAG protocol, as shown in Figure gramming offers quick and efficient design iterations and eliminates package handling. The Xilinx development sys- tem provides the programming data sequence using ...
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XC9500 In-System Programmable CPLD Family Figure 13: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable Low Power Mode All XC9500 devices offer a low-power mode for individual macrocells or across all macrocells. This feature ...
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R Combinatorial Logic Propagation Delay = T (a) T PSU Combinatorial Logic P-Term Clock Path Setup Time = T PSU (c) All resources within FB using local Feedback Combinatorial Logic Internal Cycle Time = T ( GCK ...
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XC9500 In-System Programmable CPLD Family Power-Up Characteristics The XC9500 devices are well behaved under all operating conditions. During power-up each XC9500 device employs internal circuitry which keeps the device in the quiescent state until the V supply voltage is at ...
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... Version 3.0 12/14/98 Revised datasheet to reflect new AC characteristics and Internal Timing Parmeters. 4.0 02/10/99 Corrected Figure 3. 5.0 09/15/99 Added -10 speed grade to XC95288. 5.1 09/22/03 Minor edits. 5.2 02/16/04 Corrected statement on GTS inputs on page 10. Added links to additional information. 5.3 04/15/05 Update to PDF attributes only. No changes to documentation. ...