XC95288XV-10PQ208C Xilinx Inc, XC95288XV-10PQ208C Datasheet - Page 16
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XC95288XV-10PQ208C
Manufacturer Part Number
XC95288XV-10PQ208C
Description
IC CPLD 2.5V ISP 208-PQFP
Manufacturer
Xilinx Inc
Series
XC9500XVr
Specifications of XC95288XV-10PQ208C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
2.37 V ~ 2.62 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
288
Number Of Gates
6400
Number Of I /o
168
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Voltage
2.5V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Other names
XC95288XV10PQ208C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC95288XV-10PQ208C
Manufacturer:
Xilinx Inc
Quantity:
10 000
XC9500XV Family High-Performance CPLD
Table 4: Timing Model Parameters
16
Notes:
1.
Propagation Delay
Global Clock Setup Time
Global Clock-to-output
Product Term Clock Setup
Time
Product Term
Clock-to-Output
Internal System Cycle
Period
S = the logic span of the function, as defined in the text.
Description
T
PSU
Setup Time = T
Propagation Delay = T
Combinatorial
P-Term Clock
Combinatorial
Logic
Logic
Path
(a)
PSU
(c)
Parameter
T
PD
Clock to Out Time = T
SYSTEM
T
T
T
T
T
PSU
PCO
CO
PD
SU
D/T Q
Figure 16: Basic Timing Model
www.xilinx.com
T
PCO
Product Term
Allocator
PCO
+ T
+ T
+ T
+ T
PTA
PTA
PTA
PTA
-
-
*
*
*
*
S
S
S
S
(1)
Setup Time = T
Internal System Cycle Time = T
Combinatorial
Low-Power Setting
Combinatorial
Logic
Macrocell
Logic
+ T
+ T
+ T
+ T
-
-
SU
LP
LP
LP
LP
(b)
(d)
Clock to Out Time = T
D/T Q
DS049 (v3.0) June 25, 2007
D/T Q
Product Specification
Slew-Limited
SYSTEM
DS049_16_061200
+ T
+ T
+ T
Setting
Output
T
CO
SLEW
SLEW
SLEW
-
-
-
CO
R