XCR3032XL-7PC44C Xilinx Inc, XCR3032XL-7PC44C Datasheet - Page 6

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XCR3032XL-7PC44C

Manufacturer Part Number
XCR3032XL-7PC44C
Description
IC ISP CPLD 32 MCELL3.3V 44-PLCC
Manufacturer
Xilinx Inc
Series
CoolRunner XPLA3r
Datasheet

Specifications of XCR3032XL-7PC44C

Programmable Type
In System Programmable (min 1K program/erase cycles)
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
2
Number Of Macrocells
32
Number Of Gates
750
Number Of I /o
36
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
3.3V
Memory Type
EEPROM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XCR3032XL-7PC44C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XCR3032XL-7PC44C
Manufacturer:
XILINX
0
Part Number:
XCR3032XL-7PC44C(PROG)
Manufacturer:
XILINX
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Part Number:
XCR3032XL-7PC44CES
Manufacturer:
XILINX
0
XCR3032XL 32 Macrocell CPLD
Pin Descriptions
Table 2: XCR3032XL User I/O Pins
Table 3: XCR3032XL I/O Pins
6
1.
Total User I/O Pins
Function
Block
This is an obsolete package type. It remains here for legacy
support only.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
Macrocell
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
PC44
36
PC44
(1)
13
38
32
7
11
12
14
16
17
18
19
20
21
41
40
39
37
36
34
33
4
5
6
8
9
(2)
(2)
(2)
(2)
(1)
VQ44
36
VQ44
32
26
1
7
42
43
44
10
11
12
13
14
15
35
34
33
31
30
28
27
2
3
5
6
8
(2)
(2)
(2)
(2)
CS48
CS48
D2
B1
B7
E5
36
C4
C2
C1
D3
D1
G1
G2
C5
D4
C6
D6
D7
A2
A1
E1
F1
E4
F2
F3
A6
B6
www.xilinx.com
(2)
(2)
(2)
(2)
Table 3: XCR3032XL I/O Pins
Table 4: XCR3032XL Global, JTAG, Port Enable, Power,
and No Connect Pins
Notes:
1.
2.
Notes:
1.
2.
Function
No Connects
IN0 / CLK0
IN1 / CLK1
IN2 / CLK2
IN3 / CLK3
Block
PORT_EN
Pin Type
This is an obsolete package type. It remains here for legacy
support only.
JTAG pins.
This is an obsolete package type. It remains here for legacy
support only.
Port Enable is brought High to enable JTAG pins when JTAG
pins are used as I/O. See family data sheet (DS012) for full
explanation.
2
2
2
2
2
2
2
GND
TDO
TMS
TCK
V
TDI
CC
Macrocell
10
11
12
13
14
15
16
22, 30, 42
3, 15, 23,
PC44
10
44
43
32
38
13
35
2
1
7
-
(2)
(1)
DS023 (v2.2) September 15, 2008
PC44
31
29
28
27
26
25
24
16, 24, 36
9, 17, 29,
(1)
VQ44
4
40
39
38
37
26
32
41
1
7
(2)
-
Product Specification
VQ44
25
23
22
21
20
19
18
B3, C7, E2,
A7, B2, F6,
A5, E3, E6
CS48
C3
G4
G3
A3
B4
A4
B5
E5
B1
B7
D2
CS48
G7
G6
G5
E7
F7
F5
F4
(2)
R

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