ADSP-BF527KBCZ-6C2 Analog Devices Inc, ADSP-BF527KBCZ-6C2 Datasheet - Page 58

• Manufacturer Part Number: ADSP-BF527KBCZ-6C2
• Description: IC DSP 16BIT 600MHZ 289CSPBGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF527KBCZ-6C2

• Package / Case: 289-CSPBGA
• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 600MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.10V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Cache On Chip L1/l2 Memory: 48KB
• Core Frequency Typ: 600MHz
• Dsp Type: Core
• External Supported Memory: SDRAM, SRAM, FLASH, ROM
• Interface Type: SPI, Parallel, 2 Wire
• Rohs Compliant: Yes
• Mmac: 1200
• No. Of Pins: 289
• Package: 289CSP-BGA
• Maximum Speed: 600 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Serial Peripheral Interface (SPI) Port—Slave Timing
Table 48
Table 48. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
SPICHS
SPICLS
SPICLK
HDS
SPITDS
SDSCI
SSPID
DSOE
DSDHI
DDSPID
HDSPID
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
HSPID
and
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISS Not Asserted
Sequential Transfer Delay
SPISS Assertion to First SCK Edge
Data Input Valid to SCK Edge (Data Input Setup) 1.6
SCK Sampling Edge to Data Input Invalid
SPISS Assertion to Data Out Active
SPISS Deassertion to Data High Impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
CPHA = 1
CPHA = 0
Figure 29
SPIxMISO
(OUTPUT)
SPIxMOSI
SPIxMISO
(OUTPUT)
SPIxMOSI
SPIxSCK
(INPUT)
(INPUT)
(INPUT)
(INPUT)
t
describe SPI port slave operations.
DSOE
t
DSOE
t
SDSCI
t
SSPID
t
DDSPID
t
SPICLS
Figure 29. Serial Peripheral Interface (SPI) Port—Slave Timing
t
HDSPID
Rev. B | Page 58 of 88 | May 2010
t
SPICHS
t
HDSPID
t
HSPID
Min
2 × t
2 × t
4 ×
t
2 × t
2 × t
2 × t
2.0
0
0
0
SCLK
1.8V Nominal
SCLK
SCLK
SCLK
SCLK
SCLK
ADSP-BF522/ADSP-BF524/
–1.5
V
DDEXT
–1.5
–1.5
–1.5
–1.5
–1.5
t
ADSP-BF526
DDSPID
Max Min
12.0 0
11.0 0
10
t
SSPID
2 × t
2 × t
4 × t
2 × t
2 × t
2 × t
1.6
1.6
0
2.5/3.3V Nominal
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
t
DDSPID
V
DDEXT
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
t
SPICLK
Max Min
10.3 0
8.5
10
t
HSPID
2 × t
2 × t
4 ×
t
2 × t
2 × t
2 × t
1.6
1.6
0
0
SCLK
1.8V Nominal
SCLK
SCLK
SCLK
SCLK
SCLK
ADSP-BF523/ADSP-BF525/
–1.5
V
t
HDS
DDEXT
–1.5
–1.5
–1.5
–1.5
–1.5
t
t
DSDHI
DSDHI
ADSP-BF527
Max Min
12.0 0
10
8.5
t
2 × t
2 × t
4 × t
2 × t
2 × t
2 × t
1.6
1.6
0
0
2.5/3.3V Nominal
SPITDS
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
V
DDEXT
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
Max Unit
10.3 ns
8
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns