ADSP-2184NKCA-320 Analog Devices Inc, ADSP-2184NKCA-320 Datasheet - Page 42

• Manufacturer Part Number: ADSP-2184NKCA-320
• Description: IC DSP 16BIT 80MHZ 144CSPBGA
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2184NKCA-320

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 80MHz
• Non-volatile Memory: External
• On-chip Ram: 20kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-CSPBGA
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 20KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89/3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: CSPBGA
• Package: 144CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 80 MHz
• Device Million Instructions Per Second: 80 MIPS
• Lead Free Status / Rohs Status: Not Compliant

D4/IS
ADSP-218xN
BGA PACKAGE PINOUT
The BGA package pinout is shown in
Pin names in bold text in the table replace the plain text named
functions when Mode C = 1. A + sign separates two functions
when either function can be active for either major I/O mode.
Signals enclosed in brackets [ ] are state bits latched from the
V
EINT
EC LK
G ND
G ND
G ND
EB G
D D IN T
12
D16
D14
D10
D9
E LO UT
V
G ND
G ND
D D IN T
11
D17
NC
NC
NC
NC
NC
BR
EE
D1/IAD14
V
E LIN
D D E X T
G ND
E BR
E MS
D22
D18
D15
D12
NC
10
D8
D5/IAL
D3/IACK
ERES E T
RES ET
G ND
D20
D19
D13
D11
BG
NC
NC
9
Figure 39
RFS 1/IRQ 0
D 2/IAD15
Figure 39. 144-Ball BGA Package Pinout (Bottom View)
D7/IW R
SCL K1
D6/IR D
G ND
G ND
G ND
D23
D21
NC
NC
8
and in
Rev. A | Page 42 of 48 | August 2006
TF S 1/IRQ1
[MO DE C]
[MO DE D]
Table
D 0/IAD13
DR1/FI
V
V
D D E X T
D D E X T
PF 2
PF 3
T FS0
DR 0
NC
NC
NC
7
28.
[MO DE B]
SCL K0
DT 1/FO
PWD
PF 1
G ND
G ND
DT 0
RF S 0
P MS
FL 2
NC
NC
6
value of the pin at the deassertion of RESET. The multiplexed
pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
selectable by setting Bit 10 (SPORT1 configure) of the System
Control Register. If Bit 10 = 1, these pins have serial port func-
tionality. If Bit 10 = 0, these pins are the external interrupt and
flag pins. This bit is set to 1 by default upon reset.
[MO DE A]
A7/IAD6
A9/IAD8
V
V
D D E X T
PF 0
D D IN T
DMS
G ND
G ND
FL1
NC
NC
NC
5
A 11/IAD10
A10/IAD9
A5/IAD4
V
D D E X T
IOMS
G ND
BG H
BMS
CMS
FL 0
NC
A0
4
IRQ L1 + P F6
A 12/IAD11
A8/IAD7
G ND
G ND
G ND
G ND
RD
NC
NC
NC
NC
3
IRQ 2 + PF7
A 6/IAD5
A1/IAD0
A3/IAD2
V
V
D D E X T
G ND
D D I N T
W R
NC
NC
NC
NC
2
IRQ L0 + P F5
IR QE + PF 4
A13/IAD12
CLK OUT
PW DACK
A 2/IAD1
A 4/IAD3
V
CLKIN
D D E X T
X TA L
NC
NC
1
A
B
C
D
E
F
G
H
J
K
L
M