ADSP-2189MKSTZ-300 Analog Devices Inc, ADSP-2189MKSTZ-300 Datasheet - Page 21

• Manufacturer Part Number: ADSP-2189MKSTZ-300
• Description: IC DSP CONTROLLER 16BIT 100-LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2189MKSTZ-300

• Interface: Host Interface, Serial Port
• Clock Rate: 75MHz
• Non-volatile Memory: External
• On-chip Ram: 192kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• No. Of Bits: 16
• Frequency: 77MHz
• Supply Voltage: 3.3V
• Embedded Interface Type: Host Port, Serial
• No. Of Mips: 75
• Supply Voltage Range: 2.37V To 3.6V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP-2189MKSTZ300; ADSP-2189MKSTZ300

Parameter
Bus Request–Bus Grant
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS
1
2
REV. A
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
BH
BS
SD
SDB
SE
SEC
SDBH
SEH
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.
BR Hold after CLKOUT High
BR Setup before CLKOUT Low
CLKOUT High to xMS, RD, WR Disable
xMS, RD, WR Disable to BG Low
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT High
xMS, RD, WR Disable to BGH Low
BGH High to xMS, RD, WR Enable
PMS, DMS
BMS, RD
CLKOUT
CLKOUT
BGH
WR
BG
BR
Figure 24. Bus Request–Bus Grant
t
SD
t
BH
t
t
BS
t
SDBH
SDB
1
1
–21–
2
2
t
t
SEH
Min
0.25t
0.25t
0
0
0.25t
0
0
SE
t
SEC
CK
CK
CK
+ 2
+ 10
– 3
Max
0.25t
ADSP-2189M
CK
+ 8
Unit
ns
ns
ns
ns
ns
ns
ns
ns