ADSP-2186KST-133 Analog Devices Inc, ADSP-2186KST-133 Datasheet

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... RAM and 8K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equip- ment. The ADSP-2186 is available in 100-lead LQFP and 144-Ball Mini-BGA packages. In addition, the ADSP-2186 supports new instructions, which include bit manipulations— ...

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... PC monitor software plus Assembler, Linker, Simulator and PROM Splitter software. The ADSP-218x EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your DSP software design. The EZ-KIT Lite includes the following features: • ...

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... The ADSP-2186 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2186 SPORTs. For additional information on Serial Ports, refer to the ADSP-218x DSP Hardware Reference. • SPORTs are bidirectional and have a separate, double-buffered transmit and receive section. • ...

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... SPORT configuration determined by the DSP System Control Register. Soft- ware configurable. Memory Interface Pins The ADSP-2186 processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities ...

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... CLKIN, RESET, and PF3:0 are not included in the table because these pins must be used. Setting Memory Mode Memory Mode selection for the ADSP-2186 is made during chip reset through the use of the Mode C pin. This pin is multi- Unused plexed with the DSP’s PF2 pin, so care must be taken in how Configuration the mode selection is made ...

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... In Idle mode IDMA, BDMA and autobuffer cycle steals still occur. Slow Idle The IDLE instruction is enhanced on the ADSP-2186 to let the processor’s internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a pro- grammable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction ...

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... IACK/D3 IAD15–0 16 Clock Signals The ADSP-2186 can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal operation. The only exception is while the processor is in the power-down state ...

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... The ADSP-2186 contains an 8K × 24 on-chip program RAM. The on-chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle. In addition, the ADSP-2186 allows the use of 8K external memory overlays. The program memory space organization is controlled by the Mode B pin and the PMOVLAY register ...

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... BMPAGE The byte memory space on the ADSP-2186 supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. ...

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... Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and the ADSP-2186. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’ ...

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... The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when the ADSP-2186 is ready to execute an instruction but is stopped because the external bus is already granted to another device. The other device can release the bus by deasserting bus request ...

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... ADSP-2186 BIASED ROUNDING A mode is available on the ADSP-2186 to allow biased round- ing in addition to the normal unbiased rounding. When the BIASRND bit is set to 0, the normal unbiased rounding opera- tions occur. When the BIASRND bit is set to 1, biased rounding occurs instead of the normal unbiased rounding. When operat- ...

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... RESET GND The EZ-ICE uses the EE (emulator enable) signal to take con- trol of the ADSP-2186 in the target system. This causes the processor to use its ERESET, EBR and EBG pins instead of the RESET, BR and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. ...

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... Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7 BR, CLKIN Inactive. 9 Idle refers to ADSP-2186 state of operation during execution of IDLE instruction. Deasserted pins are driven to either measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 12, 13, 14), 30% are type 2 DD and type 6, and 20% are idle instructions ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2186 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... ADSP-2186 TIMING PARAMETERS Parameter Clock Signals and Reset Timing Requirements: t CLKIN Period CKI t CLKIN Width Low CKIL t CLKIN Width High CKIH Switching Characteristics: t CLKOUT Width Low CKL t CLKOUT Width High CKH t CLKIN High to CLKOUT High CKOH Control Signals Timing Requirements: RESET Width Low ...

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... IFS IFH following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-218x DSP Hardware Reference, for further information on inter- rupt servicing.) 2 Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. ...

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... asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on 1 the following cycle. Refer to the ADSP-218x DSP Hardware Reference, for BR/BG cycle relationships. BGH is asserted when the bus is granted and the processor requires control of the bus to continue. ...

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... PMS, DMS, CMS, IOMS, BMS. CLKOUT A0–A13 DMS, PMS, BMS, IOMS, CMS RD D0–D23 WR Min Max 0 0.5 t – 0.25 t – 0.25 t – 0.25 t – 0.5 t – RDA t ASR RWR CRD t t RDD RDH t AA ADSP-2186 Unit – – 12 ...

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... ADSP-2186 Parameter Memory Write Switching Characteristics: Data Setup before WR High t DW Data Hold after WR High Pulsewidth Low to Data Enabled t WDE A0–A13, xMS Setup before WR Low t ASW Data Disable before Low t DDR CLKOUT High to WR Low t CWR A0–A13, xMS, Setup before WR Deasserted ...

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... FRAME MODE RFS OUT MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) TFS IN ALTERNATE FRAME MODE RFS IN MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) OUT SCS SCH SCDD t SCDV t SCDH t SCDE t TDE t TDV t RDV t TDE t TDV t RDV ADSP-2186 Min Max 0. SCK t SCP t SCP Unit ...

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... ADSP-2186 Parameter IDMA Address Latch Timing Requirements: t Duration of Address Latch IALP t IAD15–0 Address Setup before Address Latch End IASU t IAD15–0 Address Hold after Address Latch End IAH IACK Low before Start of Address Latch t IKA t Start of Write or Read after Address Latch End ...

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... Start of Write = IS Low and IWR Low. 1 End of Write = IS High or IWR High Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t 4 IACK IS IWR IAD15–0 Min IDSU IDH , t . IKSU IKH t IKW t IKHW t IWP t IDH t IDSU DATA ADSP-2186 Max Unit ...

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... If Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t 3 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-218x DSP Hardware Reference. 4 IACK IS IWR IAD15– ...

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... Start of Read = IS Low and IRD Low. End of Read = IS High or IRD High read or first half of PM read. 4 Second half of PM read. IACK IS IRD IAD15– IKHR t IKR t IRK t t IKDS IRDE PREVIOUS READ DATA DATA t IRDV t IRDH ADSP-2186 Min Max Unit 0.5 t – – – IKDH t IKDD ...

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... ADSP-2186 Parameter IDMA Read, Short Read Cycle Timing Requirements: IACK Low before Start of Read t IKR t Duration of Read (DM, PM1) IRP1 t Duration of Read (PM2) IRP2 Switching Characteristics: IACK High after Start of Read t IKHR t IAD15–0 Data Hold after End of Read IKDH t IAD15–0 Data Disabled after End of Read ...

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... MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL DD MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 4 IDLE REFERS TO ADSP-2186 STATE OF OPERATION DURING EXECUTION OF IDLE 2 INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V f × 20 MHz = 35 mW × ...

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... ADSP-2186 CAPACITIVE LOADING Figures 24 and 25 show the capacitive loading characteristics of the ADSP-2186 + 4. 100 150 200 C – NOMINAL –2 –4 – 100 150 C – TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state ...

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... AMB CASE CA Case Temperature in ° CASE PD = Power Dissipation in W θ = Thermal Resistance (Case-to-Ambient) CA θ = Thermal Resistance (Junction-to-Ambient) JA θ = Thermal Resistance (Junction-to-Case) JC Package JA LQFP 50°C/W 2°C/W Mini-BGA 70.7°C/W 7.4°C/W 10k 1k 100 48°C/W 63.3°C ADSP-2186 100 120 TEMPERATURE – C ...

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... A11/IAD10 9 A12/IAD11 10 A13/IAD12 11 GND 12 CLKIN 13 XTAL 14 VDD 15 CLKOUT 16 GND 17 VDD BMS 21 DMS 22 PMS 23 IOMS 24 CMS 25 100-Lead LQFP Package Pinout ADSP-2186 TOP VIEW (Not to Scale) 75 D15 74 D14 D13 73 72 D12 71 GND 70 D11 69 D10 VDD 66 GND D7/IWR 63 D6/IRD D5/IAL 62 61 D4/IS 60 GND 59 VDD ...

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... The ADSP-2186 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. ...

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... NC D15 GND NC D12 D10 GND VDD D4 GND NC GND VDD VDD D1/IAD14 EBG BR EBR EINT ELOUT ELIN EMS ECLK EE ADSP-2186 Mini-BGA (CA) Package Pinout Bottom View GND NC D20 D23 VDD GND NC PWD D19 D21 VDD A7/IAD6 PF2 PF1 D13 NC A9/IAD8 [MODE C] [MODE B] PF0 ...

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... The ADSP-2186 Mini-BGA package pinout is shown in the table below. Pin names in bold text replace the plain text named func- tions when Mode sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. ...

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... ADSP-2186 COPLANARITY NOTE: THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. OUTLINE DIMENSIONS Dimensions shown in millimeters. 100-Lead Metric Thin Plastic Quad Flatpack (LQFP) (ST-100) 16.20 16.00 SQ 15.80 14.05 1.60 MAX 14.00 SQ 0.75 13.95 ...

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... RELATIVE TO THE BALL POPULATION. Ambient Temperature Part Number Range ADSP-2186KST-115 0°C to 70°C ADSP-2186BST-115 –40°C to +85°C ADSP-2186KST-133 0°C to 70°C ADSP-2186BST-133 –40°C to +85°C ADSP-2186KST-160 0°C to 70°C ADSP-2186BST-160 –40°C to +85°C ADSP-2186BCA-160 –40°C to +85° Plastic Thin Quad Flatpack (LQFP) ...

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