ADSP-21991BST Analog Devices Inc, ADSP-21991BST Datasheet - Page 12

• Manufacturer Part Number: ADSP-21991BST
• Description: IC DSP CONTROLLER 16BIT 176LQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-21991BST

• Rohs Status: RoHS non-compliant
• Interface: SPI, SSP
• Clock Rate: 160MHz
• Non-volatile Memory: External
• On-chip Ram: 112kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP

ADSP-21991
To exit Power-Down Core mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions.
Power-Down Core/Peripherals Mode
When the ADSP-21991 is in Power-Down Core/Peripherals
mode, the DSP core clock and peripheral bus clock are off, but
the DSP keeps the PLL running. The DSP does not retain the
contents of the instruction pipeline.The peripheral bus is
stopped, so the peripherals cannot receive data.
To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after five to six cycles of latency) resumes
executing instructions.
Power-Down All Mode
When the ADSP-21991 is in Power-Down All mode, the DSP
core clock, the peripheral clock, and the PLL are all stopped. The
DSP does not retain the contents of the instruction pipeline. The
peripheral bus is stopped, so the peripherals cannot receive data.
To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after 500 cycles to re-stabilize the PLL)
resumes executing instructions.
Clock Signals
The ADSP-21991 can be clocked by a crystal oscillator or a
buffered, shaped clock derived from an external clock oscillator.
If a crystal oscillator is used, the crystal should be connected
across the CLKIN and XTAL pins, with two capacitors
connected as shown in
on crystal type and should be specified by the crystal manufac-
turer. A parallel resonant, fundamental frequency,
microprocessor grade crystal should be used for this
configuration.
If a buffered, shaped clock is used, this external clock connects
to the DSP CLKIN pin. CLKIN input cannot be halted,
changed, or operated below the specified frequency during
normal operation. This clock signal should be a TTL compatible
signal. When an external clock is used, the XTAL input must be
left unconnected.
The DSP provides a user programmable 1 to 32 multiplica-
tion of the input clock, including some fractional values, to
support 128 external to internal (DSP core) clock ratios. The
BYPASS pin, and MSEL6–0 and DF bits, in the PLL configu-
ration register, decide the PLL multiplication factor at reset. At
run time, the multiplication factor can be controlled in software.
To support input clocks greater that 100 MHz, the PLL uses an
additional bit (DF). If the input clock is greater than 100 MHz,
DF must be set. If the input clock is less than 100 MHz, DF must
be cleared. For clock multiplier settings, see the ADSP-2199x
Mixed Signal DSP Controller Hardware Reference.
The peripheral clock is supplied to the CLKOUT pin.
All on-chip peripherals for the ADSP-21991 operate at the rate
set by the peripheral clock. The peripheral clock (HCLK) is
either equal to the core clock rate or one half the DSP core clock
rate (CCLK). This selection is controlled by the IOSEL bit in
the PLLCTL register. The maximum core clock is 160 MHz for
the ADSP-21991BST and 150 MHz for the ADSP-21991BBC.
Figure
5. Capacitor values are dependent
–12–
The maximum peripheral clock is 80 MHz for the ADSP-
21991BST and 75 MHz for the ADSP-21991BBC—the combi-
nation of the input clock and core/peripheral clock ratios may not
exceed these limits.
Reset and Power-On Reset (POR)
The RESET pin initiates a complete hardware reset of the ADSP-
21991 when pulled low. The RESET signal must be asserted
when the device is powered up to assure proper initialization. The
ADSP-21991 contains an integrated power-on reset (POR)
circuit that provides an output reset signal, POR, from the ADSP-
21991 on power-up and if the power supply voltage falls below
the threshold level. The ADSP-21991 may be reset from an
external source using the RESET signal, or alternatively, the
internal power-on reset circuit may be used by connecting the
POR pin to the RESET pin. During power-up the RESET line
must be activated for long enough to allow the DSP core’s internal
clock to stabilize. The power-up sequence is defined as the total
time required for the crystal oscillator to stabilize after a valid
VDD is applied to the processor and for the internal phase-locked
loop (PLL) to lock onto the specific crystal frequency. A
minimum of 512 cycles will ensure that the PLL has locked (this
does not include the crystal oscillator start-up time).
The RESET input contains some hysteresis. If an RC circuit is
used to generate the RESET signal, the circuit should use an
external Schmitt trigger.
The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts, and resets all registers to their
default values (where applicable). When RESET is released, if
there is no pending bus request, program control jumps to the
location of the on-chip boot ROM (0xFF0000) and the booting
sequence is performed.
Power Supplies
The ADSP-21991 has separate power supply connections for the
internal (V
internal supply must meet the 2.5 V requirement. The external
supply must be connected to a 3.3 V supply. All external supply
pins must be connected to the same supply. The ideal power-on
sequence for the DSP is to provide power-up of all supplies simul-
taneously. If there is going to be some delay in power-up between
the supplies, provide V
Figure 5. External Crystal Connections
DDINT
) and external (V
CLKIN
DD
ADSP-2199x
first, then V
XTAL
DDEXT
DD_IO
) power supplies. The
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