ADSP-21061LAS-176 Analog Devices Inc, ADSP-21061LAS-176 Datasheet - Page 27

• Manufacturer Part Number: ADSP-21061LAS-176
• Description: IC DSP CONTROLLER 32BIT 240MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061LAS-176

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 44MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 44MHz
• Mips: 44
• Device Input Clock Speed: 44MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory sys-
tems that require CLKIN—relative timing or for accessing a
slave ADSP-21061 (in multiprocessor memory space). These
synchronous switching characteristics are also valid during
asynchronous memory reads and writes except where noted (see
Memory Read—Bus Master on Page 25
Table 14. Synchronous Read/Write—Bus Master
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t
The falling edge of MSx, SW, BMS is referenced.
ACK delay/setup: User must meet t
See
SSDATI
HSDATI
DAAK
SACKC
HACK
DADRO
HADRO
DPGC
DRDO
DWRO
DRWL
SDDATO
DATTR
DADCCK
ADRCK
ADRCKH
ADRCKL
(high).
Example System Hold Time Calculation on Page 44
Data Setup Before CLKIN
(50 MHz, t
Data Hold After CLKIN
ACK Delay After Address, Selects
ACK Setup Before CLKIN
ACK Hold After CLKIN
Address, MSx, BMS, SW Delay After CLKIN
Address, MSx, BMS, SW Hold After CLKIN
PAGE Delay After CLKIN
RD High Delay After CLKIN
WR High Delay After CLKIN
(50 MHz, t
RD/WR Low Delay After CLKIN
Data Delay After CLKIN
Data Disable After CLKIN
ADRCLK Delay After CLKIN
ADRCLK Period
ADRCLK Width High
ADRCLK Width Low
DAAK
CK
CK
= 20 ns)
= 20 ns)
or t
DSAK
1
and
or synchronous specification t
3
4
Memory Write—
for calculation of hold times given capacitive and dc loads.
2, 3
Rev. C | Page 27 of 56 | July 2007
2
SAKC
CK
< 25 ns. For all other devices, use the preceding timing specification of the same name.
for deassertion of ACK (low), all three specifications must be met for assertion of ACK
Bus Master on Page
these switching characteristics must meet the slave’s timing
requirements for synchronous read/writes (see
Read/Write—Bus Slave on Page
must also meet these (bus master) timing requirements for data
and acknowledge setup and hold times.
Min
2 + DT/8
1.5 + DT/8
3.5 – DT/8
6.5+DT/4
–1 – DT/4
–1 – DT/8
9 + DT/8
–1.5 – DT/8
–2.5 – 3DT/16
–1.5 – 3DT/16
8 + DT/4
0 – DT/8
(t
(t
4 + DT/8
t
CK
CK
CK
26). When accessing a slave ADSP-21061,
/2 – 2)
/2 – 2)
ADSP-21061/ADSP-21061L
5 V and 3.3 V
29). The slave ADSP-21061
Max
15 + 7DT/8 + W
6.5 – DT/8
16 + DT/8
4 – DT/8
4 – 3DT/16
4 – 3DT/16
12 + DT/4
19 + 5DT/16
7 – DT/8
10 + DT/8
Synchronous
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns