ADSP-2171BS-133 Analog Devices Inc, ADSP-2171BS-133 Datasheet - Page 15

• Manufacturer Part Number: ADSP-2171BS-133
• Description: IC DSP CONTROLLER 16BIT 128PQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2171BS-133

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 33MHz
• Non-volatile Memory: External
• On-chip Ram: 10kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 33.33MHz
• Mips: 33
• Device Input Clock Speed: 33.33MHz
• Ram Size: 10KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

Biased Rounding
A new mode allows biased rounding in addition to the normal
unbiased rounding. When the BIASRND bit is set to 0, the nor-
mal unbiased rounding operations occur. When the BIASRND
bit is set to 1, biased rounding occurs instead of the normal un-
biased rounding. When operating in biased rounding mode all
rounding operations with MR0 set to 0x8000 will round up,
rather than only rounding odd MR1 values up. For example:
MR value before RND
00-0000-8000
00-0001-8000
00-0000-8001
00-0001-8001
00-0000-7FFF
00-0001-7FFF
This mode only has an effect when the MR0 register contains
0x8000, all other rounding operation work normally. This mode
was added to allow more efficient implementation of bit speci-
fied algorithms which specify biased rounding such as the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer
REV. A
Control register.
2171 HDR5 Write
2171 HDR4 Write
2171 HDR3 Write
2171 HDR2 Write
2171 HDR1 Write
2171 HDR0 Write
Overwrite Mode
Software Reset
biased RND result unbiased RND result
00-0001-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
15 14 13 12 11 10
15 14 13 12 11 10
0
0
0
0
0
0
00-0000-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
0
0
0
0
0
0
Control Registers
0
9
9
0
0x3FE6
0x3FE7
0
8
1
8
HSR6
HSR7
–15–
7
0
7
0
INSTRUCTION SET DESCRIPTION
The ADSP-217x assembly language instruction set has an alge-
braic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:
Consult the ADSP-2100 Family User’s Manual for a complete
description of the syntax and an instruction set reference.
The algebraic syntax eliminates the need to remember cryptic
Every instruction assembles into a single, 24-bit word that can
The syntax is a superset ADSP-2100 Family assembly lan-
Sixteen condition codes are available. For conditional jump,
Multifunction instructions allow parallel execution of an arith-
6
0
0
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
execute in a single instruction cycle.
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize internal memory and conform to the ADSP-
217x’s interrupt vector and reset vector map.
call, return, or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
metic instruction with up to two fetches or one write to pro-
cessor memory space during a single instruction cycle.
6
ADSP-2171/ADSP-2172/ADSP-2173
0
5
5
0
4
0
0
4
0
3
3
0
2
0
2
0
0
1
0
1
0
0
0
0
Host HDR0 Write
Host HDR1 Write
Host HDR2 Write
Host HDR3 Write
Host HDR4 Write
Host HDR5 Write
2171 HDR0 Write
2171 HDR1 Write
2171 HDR2 Write
2171 HDR3 Write
2171 HDR4 Write
2171 HDR5 Write