ADSP-2173BST-80 Analog Devices Inc, ADSP-2173BST-80 Datasheet - Page 12

• Manufacturer Part Number: ADSP-2173BST-80
• Description: IC DSP CONTROLLER 16BIT 128TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2173BST-80

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 20MHz
• Non-volatile Memory: External
• On-chip Ram: 10kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 20MHz
• Mips: 20
• Device Input Clock Speed: 20MHz
• Ram Size: 10KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

ADSP-2171/ADSP-2172/ADSP-2173
Internal Serial Clock Generation ISCLK
Transmit Frame Sync Required TFSR
(or MCL Multichannel Length; 1 = 32 words, 0 = 24 words
Receive Frame Sync Required RFSR
15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPORT0 Multichannel Receive Word Enable Registers
Only If Multichannel Mode Enabled
Transmit Frame Sync Width TFSW
Receive Frame Sync Width RFSW
Multichannel Frame Delay MFD
Multichannel Enable MCE
ITFS Internal Transmit Frame Sync Enable
1 = Channel Enabled
0 = Channel Ignored
Only If Multichannel Mode Enabled)
9
0x3FFA
0x3FF9
8
15 14 13 12 11 10
0
7
1
6
DWAIT4
15 14 13 12 11 10
5
0
1
4
ROM Enable/Data Memory Wait State
0
1
3
ROM enable
1 = enable
0 = disable
0
1
DWAIT3
2
0
1
1
Control Register
Control Registers
0
9
1
SPORT0 Control Register
0
0x3FFE
0
8
1
DWAIT2
–12–
9
0
7
1
0x3FF6
SPORT0 Multichannel Transmit Word Enable Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10
8
0
1
6
7
0
5
1
DWAIT1
6
0
1
4
0
5
1
3
4
0
2
1
DWAIT0
DTYPE Data Format
00 = right justify, zero-fill unused MSBs
01 = right justify, sign extend into unused MSBs
10 = compand using -law
11 = compand using A-law
INVRFS Invert Receive Frame Sync
INVTFS Invert Transmit Frame Sync
(or INVTDV Invert Transmit Data Valid
IRFS Internal Receive Frame Sync Enable
Only If Multichannel Mode Enabled)
1 = Channel Enabled
0 = Channel Ignored
0
3
1
1
9
0
2
0
1
0x3FF8
0x3FF7
8
1
0
7
SLEN Serial Word Length
0
0
6
5
4
3
2
1
REV. A
0