ADSP-2186KST-160 Analog Devices Inc, ADSP-2186KST-160 Datasheet - Page 2
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ADSP-2186KST-160
Manufacturer Part Number
ADSP-2186KST-160
Description
IC DSP CONTROLLER 16BIT 100LQFP
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet
1.ADSP-2186BSTZ-160.pdf
(36 pages)
Specifications of ADSP-2186KST-160
Rohs Status
RoHS non-compliant
Interface
Host Interface, Serial Port
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
40kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Device Core Size
16b
Format
Fixed Point
Clock Freq (max)
40MHz
Mips
40
Device Input Clock Speed
40MHz
Ram Size
40KB
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-2186KST-160
Manufacturer:
AD
Quantity:
7
SoundPort and EZ-ICE are registered trademarks of Analog Devices, Inc.
ADSP-2186
Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2186 operates with a 25 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
The ADSP-2186’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADSP-2186 can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
Development System
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADSP-2186. The System Builder provides a high level
method for defining the architecture of systems under develop-
ment. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction-
level simulation with a reconfigurable user interface to display
different portions of the hardware environment. A PROM
Splitter generates PROM programmer compatible files. The
C Compiler, based on the Free Software Foundation’s GNU
C Compiler, generates ADSP-2186 assembly source code.
The source code debugger allows programs to be corrected in
the C environment. The Runtime Library includes over 100
ANSI-standard mathematical and DSP-specific functions.
The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the ADSP-218x family: an ADSP-
218x-based evaluation board with PC monitor software plus
Assembler, Linker, Simulator and PROM Splitter software. The
ADSP-218x EZ-KIT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP
software design. The EZ-KIT Lite includes the following features:
• 75 MHz ADSP-2189M
• Full 16-bit Stereo Audio I/O with AD73322 Codec
• RS-232 Interface
• EZ-ICE Connector for Emulator Control
• DSP Demo Programs
• Evaluation Suite of Visual DSP
The ADSP-218x EZ-ICE Emulator aids in the hardware debug-
ging of an ADSP-2186 system. The emulator consists of hard-
ware, host computer resident software, and the target board
connector. The ADSP-2186 integrates on-chip emulation sup-
port with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection that requires fewer mechanical
clearance considerations than other ADSP-2100 Family EZ-
ICEs. The ADSP-2186 device need not be removed from the
target system when using the EZ-ICE, nor are any adapters
needed. Due to the small footprint of the EZ-ICE connector,
emulation can be supported in final board designs.
The EZ-ICE performs a full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
See Designing An EZ-ICE-Compatible Target System in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as
well as the Target Board Connector for EZ-ICE Probe section
of this data sheet, for the exact specifications of the EZ-ICE
target board connector.
Additional Information
This data sheet provides a general overview of ADSP-2186
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-218x DSP
Hardware Reference. For more information about the develop-
ment tools, refer to the ADSP-2100 Family Development Tools
Data Sheet.
ARCHITECTURE OVERVIEW
The ADSP-2186 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single
processor cycle. The ADSP-2186 assembly language uses an
algebraic syntax for ease of coding and readability. A compre-
hensive set of development tools supports program development.
Figure 1 is an overall block diagram of the ADSP-2186. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
nent operations.
The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
DATA ADDRESS
GENERATORS
DAG 1
ALU
ARITHMETIC UNITS
ADSP-2100 BASE
ARCHITECTURE
DAG 2
MAC
SHIFTER
SEQUENCER
PROGRAM
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
PROGRAM MEMORY ADDRESS
PROGRAM
MEMORY
SPORT 0
8K
SERIAL PORTS
POWER-DOWN
24
CONTROL
MEMORY
SPORT 1
MEMORY
8K
DATA
16
PROGRAMMABLE
TIMER
FLAGS
AND
I/O
FULL MEMORY
CONTROLLER
EXTERNAL
EXTERNAL
EXTERNAL
INTERNAL
ADDRESS
HOST MODE
BYTE DMA
DATA
DATA
PORT
BUS
DMA
BUS
BUS
MODE
OR