EP1K10TC100-3N Altera, EP1K10TC100-3N Datasheet - Page 10
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EP1K10TC100-3N
Manufacturer Part Number
EP1K10TC100-3N
Description
IC ACEX 1K FPGA 10K 100-TQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet
1.EP1K10TC100-3N.pdf
(86 pages)
Specifications of EP1K10TC100-3N
Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
66
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Family Name
ACEX™ 1K
Number Of Usable Gates
10000
Number Of Logic Blocks/elements
576
# I/os (max)
66
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
576
Ram Bits
12288
Device System Gates
56000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1828
EP1K10TC100-3N
EP1K10TC100-3N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1K10TC100-3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 2. ACEX 1K Device in Dual-Port RAM Mode
Notes:
(1)
(2)
10
EAB Local
Interconnect (2)
All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.
wraddress[ ]
rdaddress[ ]
outclocken
inclocken
outclock
inclock
data[ ]
wren
rden
Dedicated Clocks
Dedicated Inputs &
Global Signals
2
4
The EAB can use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in
ACEX 1K EAB can also be used in a single-port mode (see
D
ENA
D
ENA
D
ENA
Q
Q
Q
Note (1)
D
ENA
D
ENA
Generator
Row Interconnect
Pulse
Write
Q
Q
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Data In
Read Address
Write Address
Read Enable
Write Enable
RAM/ROM
1,024
2,048
256
Data Out
512
16
8
4
2
D
ENA
Q
4, 8, 16, 32
Column Interconnect
Altera Corporation
4, 8, 16, 32
Figure
Figure
4, 8
4).
3. The