EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 44

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

Page 44
Validating Pin Placement
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The .pof and .jic files are used with the Quartus II Programmer to program the
configuration devices while the .hexout, .rbf, .ttf, and .rpd files are used with other
programmers.
When working with multi-device configuration chains, you should combine each
device’s .sof file into one configuration file in the Convert Programming Files dialog
box. When generating the configuration file, ensure that the configuration files are in
the same order as the devices on the board.
For more information about setting device configuration options or creating
configuration files, refer to the
Configuration Handbook.
For more information about programming file formats and using the programmer,
refer to the
After creating pin-related assignments, you must validate the assignments against
rules specific to the Cyclone III device. This section discusses the validation and
considerations about pin placement.
I/O Assignment Analysis
The Start I/O Assignment Analysis command allows you to check the legality of
your I/O assignments before, during, or after you compile your design. If design files
are available, you can use this command to perform thorough legality checks on your
design’s I/O pins and surrounding logic. These checks include proper reference
voltage pin usage, valid pin location assignments, and acceptable mixed I/O
standards. Run the analysis each time you add or modify a pin-related assignment.
For more information about the Start I/O Assignment Analysis command and its
design flow, refer to the
Handbook.
DC Guidelines
Sourcing or sinking large amounts of steady current from output pins can damage the
device due to electromigration, where the movement of the conducting metal's atoms
is caused by the large amount of electric current flowing through it. Some examples
pull a high output pin to ground or connect a low output pin to V
maximum DC current a Cyclone III I/O pin can sink is 25 mA and source is 40 mA. If
certain pins have to be pulled high or low, pull them through external resistors.
Tabular Text File (.ttf),
Raw Programming Data (.rpd) file, and
JTAG Indirect Configuration File (.jic).
Quartus II Programmer
I/O Management
Software Settings
chapter in volume 3 of the Quartus II Handbook.
chapter in volume 2 of the Quartus II
section in volume 2 of the
© November 2008 Altera Corporation
CC
Design and Compilation
directly. The