EP1C3T100C6N Altera, EP1C3T100C6N Datasheet - Page 9
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EP1C3T100C6N
Manufacturer Part Number
EP1C3T100C6N
Description
IC CYCLONE FPGA 2910 LE 100-TQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C3T100C6N
Number Of Logic Elements/cells
2910
Number Of Labs/clbs
291
Total Ram Bits
59904
Number Of I /o
65
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Family Name
Cyclone®
Number Of Logic Blocks/elements
2910
# I/os (max)
65
Frequency (max)
405.2MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
2910
Ram Bits
59904
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1799
EP1C3T100C6N
EP1C3T100C6N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C3T100C6N
Manufacturer:
ALTERA
Quantity:
241
Logic Array
Blocks
Figure 2–2. Cyclone LAB Structure
Altera Corporation
May 2008
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local
interconnect, look-up table (LUT) chain, and register chain connection
lines. The local interconnect transfers signals between LEs in the same
LAB. LUT chain connections transfer the output of one LE's LUT to the
adjacent LE for fast sequential LUT connections within the same LAB.
Register chain connections transfer the output of one LE's register to the
adjacent LE's register within a LAB. The Quartus
associated logic within a LAB or adjacent LABs, allowing the use of local,
LUT chain, and register chain connections for performance and area
efficiency.
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM
blocks from the left and right can also drive a LAB's local interconnect
through the direct link connection. The direct link connection feature
minimizes the use of row and column interconnects, providing higher
Figure 2–2
LAB
details the Cyclone LAB.
Local Interconnect
Row Interconnect
®
II Compiler places
Logic Array Blocks
Column Interconnect
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Preliminary
2–3