EPF6010ATC100-3N Altera, EPF6010ATC100-3N Datasheet - Page 23

• Manufacturer Part Number: EPF6010ATC100-3N
• Description: IC FLEX 6000 FPGA 10K 100-TQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6010ATC100-3N

• Number Of Logic Elements/cells: 880
• Number Of Labs/clbs: 88
• Number Of I /o: 71
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Total Ram Bits: -
• Other names: 544-1950; EPF6010ATC100-3N

Altera Corporation
I/O Elements
An IOE contains a bidirectional I/O buffer and a tri-state buffer. IOEs can
be used as input, output, or bidirectional pins. An IOE receives its data
signals from the adjacent local interconnect, which can be driven by a row
or column interconnect (allowing any LE in the device to drive the IOE) or
by an adjacent LE (allowing fast clock-to-output delays). A FastFLEX
I/O pin is a row or column output pin that receives its data signals from
the adjacent local interconnect driven by an adjacent LE. The IOE receives
its output enable signal through the same path, allowing individual
output enables for every pin and permitting emulation of open-drain
buffers. The Altera Compiler uses programmable inversion to invert the
data or output enable signals automatically where appropriate. Open-
drain emulation is provided by driving the data input low and toggling
the OE of each IOE. This emulation is possible because there is one OE per
pin.
A chip-wide output enable feature allows the designer to disable all pins
of the device by asserting one pin (DEV_OE). This feature is useful during
board debugging or testing.
Figure 12
Figure 12. IOE Block Diagram
shows the IOE block diagram.
Chip-Wide Output Enable
From LAB Local Interconnect
From LAB Local Interconnect
To Row or Column Interconnect
FLEX 6000 Programmable Logic Device Family Data Sheet
Delay
Slew-Rate
Control
TM
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