EP1C3T144C6 Altera, EP1C3T144C6 Datasheet - Page 34
![IC CYCLONE FPGA 2910 LE 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EP1C3T144C6
Manufacturer Part Number
EP1C3T144C6
Description
IC CYCLONE FPGA 2910 LE 144-TQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C3T144C6
Number Of Logic Elements/cells
2910
Number Of Labs/clbs
291
Total Ram Bits
59904
Number Of I /o
104
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1050
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C3T144C6
Manufacturer:
ALTERA
Quantity:
70
Company:
Part Number:
EP1C3T144C6
Manufacturer:
ALTERA
Quantity:
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Part Number:
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Manufacturer:
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Company:
Part Number:
EP1C3T144C6N
Manufacturer:
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Quantity:
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Part Number:
EP1C3T144C6N
Manufacturer:
ALTERA
Quantity:
20 000
Cyclone Device Handbook, Volume 1
Figure 2–20. Read/Write Clock Mode in Simple Dual-Port Mode
Notes to
(1)
(2)
2–28
Preliminary
wraddress[ ]
address[ ]
byteena[ ]
wrclken
wrclock
rdclken
rdclock
All registers shown except the rden register have asynchronous clear ports.
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
data[ ]
wren
rden
Figure
6 LAB Row
Clocks
6
2–20:
Read/Write Clock Mode
The M4K memory blocks implement read/write clock mode for simple
dual-port memory. You can use up to two clocks in this mode. The write
clock controls the block's data inputs, wraddress, and wren. The read
clock controls the data output, rdaddress, and rden. The memory
blocks support independent clock enables for each clock and
asynchronous clear signals for the read- and write-side registers.
Figure 2–20
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
shows a memory block in read/write clock mode.
Q
Q
Q
Q
Q
Q
Generator
Pulse
Write
Data In
Read Address
Write Address
Byte Enable
Read Enable
Write Enable
Notes
Memory Block
1,024 × 4
2,048 × 2
4,096 × 1
Data Out
256 × 16
512 × 8
(1),
(2)
D
ENA
Q
Altera Corporation
To MultiTrack
Interconnect
May 2008