EP2C8T144I8N Altera, EP2C8T144I8N Datasheet - Page 84
![IC CYCLONE II FPGA 8K 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EP2C8T144I8N
Manufacturer Part Number
EP2C8T144I8N
Description
IC CYCLONE II FPGA 8K 144-TQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C8T144I8N
Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
85
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
85
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2157
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C8T144I8N
Manufacturer:
ALTERA31
Quantity:
387
Part Number:
EP2C8T144I8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Cyclone II Hot-Socketing Specifications
4–2
Cyclone II Device Handbook, Volume 1
Devices Can Be Driven before Power-Up
You can drive signals into the I/O pins, dedicated input pins, and
dedicated clock pins of Cyclone II devices before or during power-up or
power-down without damaging the device. Cyclone II devices support
any power-up or power-down sequence (V
system level design.
I/O Pins Remain Tri-Stated during Power-Up
A device that does not support hot socketing may interrupt system
operation or cause contention by driving out before or during power-up.
In a hot-socketing situation, the Cyclone II device’s output buffers are
turned off during system power-up or power-down. The Cyclone II
device also does not drive out until the device is configured and has
attained proper operating conditions. The I/O pins are tri-stated until the
device enters user mode with a weak pull-up resistor (R) to 3.3V. Refer to
Figure 4–1
1
■
■
This specification takes into account the pin capacitance but not board
trace and external loading capacitance. You must consider additional
capacitance for trace, connector, and loading separately.
I
specification applies when all V
powered-up or powered-down conditions. For the AC specification, the
peak current duration due to power-up transients is 10 ns or less.
A possible concern for semiconductor devices in general regarding hot
socketing is the potential for latch-up. Latch-up can occur when electrical
subsystems are hot socketed into an active system. During hot socketing,
the signal pins may be connected and driven by the active system before
IOPIN
The hot-socketing DC specification is | I
The hot-socketing AC specification is | I
less.
is the current at any user I/O pin on the device. The DC
You can power up or power down the V
any sequence. The V
to their steady state levels. (Refer to
information.) The power supply ramp rates can range from
100 µs to 100 ms for non “A” devices. Both V
power down within 100 ms of each other to prevent I/O pins
from driving out. During hot socketing, the I/O pin capacitance
is less than 15 pF and the clock pin capacitance is less than 20 pF.
Cyclone II devices meet the following hot-socketing
specification.
for more information.
CCIO
CC
and V
supplies to the device are stable in the
CCINT
CCIO
IOPIN
IOPIN
Figure 4–3
must have monotonic rise
and V
CCIO
| < 300 µA.
| < 8 mA for 10 ns or
and V
CCINT
CC
Altera Corporation
for more
supplies must
February 2007
) to simplify
CCINT
pins in