EP3C10E144I7N Altera, EP3C10E144I7N Datasheet - Page 29
![IC CYCLONE III FPGA 10K 144 EQFP](/photos/6/72/67252/ep3c10e144i7n_sml.jpg)
EP3C10E144I7N
Manufacturer Part Number
EP3C10E144I7N
Description
IC CYCLONE III FPGA 10K 144 EQFP
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
Specifications of EP3C10E144I7N
Number Of Logic Elements/cells
10320
Number Of Labs/clbs
645
Total Ram Bits
423936
Number Of I /o
94
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-EQFP
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2535
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C10E144I7N
Manufacturer:
ALTERA31
Quantity:
365
Chapter 1: Cyclone III Device Data Sheet
Glossary
Table 1–39. Glossary (Part 3 of 5)
© January 2010 Altera Corporation
Letter
R
S
R
Receiver Input
Waveform
RSKM (Receiver
input skew
margin)
Single-ended
Voltage
referenced I/O
Standard
SW (Sampling
Window)
L
Term
Receiver differential input discrete resistor (external to Cyclone III devices).
Receiver Input Waveform for LVDS and LVPECL Differential Standards.
HIGH-SPEED I/O Block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
V
V
OH
OL
V
CM
V
ID
V
ID
Definitions
V
REF
Cyclone III Device Handbook, Volume 2
V
ID
Positive Channel (p) = V
Negative Channel (n) = V
Ground
0 V
p - n
V
V
IH(DC)
IL(DC)
V
V
IH ( AC )
IL(AC )
V
CCIO
V
IH
IL
SS
1–29