EP3C5U256I7N Altera, EP3C5U256I7N Datasheet - Page 109
EP3C5U256I7N
Manufacturer Part Number
EP3C5U256I7N
Description
IC CYCLONE III FPGA 5K 256 UBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C5U256I7N.pdf
(274 pages)
Specifications of EP3C5U256I7N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-UBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
182
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
UFBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2560
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5U256I7N
Manufacturer:
ALTERA21
Quantity:
201
Part Number:
EP3C5U256I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Chapter 6: I/O Features in the Cyclone III Device Family
OCT Support
© December 2009
Altera Corporation
Figure 6–3
Figure 6–3. Cyclone III Device Family OCT Block Placement
Each calibration block comes with a pair of RUP and RDN pins. When used for
calibration, the RUP pin is connected to V
50-Ω ±1% resistor for an on-chip series termination value of 25 Ω or 50 Ω,
respectively. The RDN pin is connected to GND through an external 25-Ω ±1% or 50-Ω
The external resistors are compared with the internal resistance using comparators.
The resultant outputs of the comparators are used by the OCT calibration block to
dynamically adjust buffer impedance.
During calibration, the resistance of the RUP and RDN pins varies. For an estimate of
the maximum possible current through the external calibration resistors, assume a
minimum resistance of 0 Ω on the RUP and RDN pins during calibration.
±1% resistor for an on-chip series termination value of 25 Ω or 50 Ω, respectively.
shows the top-level view of the OCT calibration blocks placement.
I/O Bank 3
I/O Bank 8
Cyclone III Device Family
I/O Bank 4
I/O Bank 7
CCIO
through an external 25-Ω ±1% or
Cyclone III Device Handbook, Volume 1
I/O bank with
calibration block
I/O bank without
calibration block
Calibration block
coverage
6–9
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