EP1K100QC208-1N Altera, EP1K100QC208-1N Datasheet - Page 7
![IC ACEX 1K FPGA 100K 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EP1K100QC208-1N
Manufacturer Part Number
EP1K100QC208-1N
Description
IC ACEX 1K FPGA 100K 208-PQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet
1.EP1K10TC100-3N.pdf
(86 pages)
Specifications of EP1K100QC208-1N
Number Of Logic Elements/cells
4992
Number Of Labs/clbs
624
Total Ram Bits
49152
Number Of I /o
147
Number Of Gates
257000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Logic Type
Programmable Logic Device (PLD)
No. Of I/o's
147
Frequency
180MHz
Supply Current Max
25mA
Operating Temperature Range
0°C To +70°C
Logic Case Style
QFP
No. Of Pins
208
Rohs Compliant
Yes
Family Name
ACEX™ 1K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4992
# I/os (max)
147
Frequency (max)
333.33MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
4992
Ram Bits
49152
Device System Gates
257000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1823
EP1K100QC208-1N
EP1K100QC208-1N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1K100QC208-1N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
ACEX 1K Programmable Logic Device Family Data Sheet
The logic array consists of logic array blocks (LABs). Each LAB contains
eight LEs and a local interconnect. An LE consists of a 4-input LUT, a
programmable flipflop, and dedicated signal paths for carry and cascade
functions. The eight LEs can be used to create medium-sized blocks of
logic—such as 8-bit counters, address decoders, or state machines—or
combined across LABs to create larger logic blocks. Each LAB represents
about 96 usable logic gates.
Signal interconnections within ACEX 1K devices (as well as to and from
device pins) are provided by the FastTrack Interconnect routing structure,
which is a series of fast, continuous row and column channels that run the
entire length and width of the device.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect routing structure. Each IOE
contains a bidirectional I/O buffer and a flipflop that can be used as either
an output or input register to feed input, output, or bidirectional signals.
When used with a dedicated clock pin, these registers provide exceptional
performance. As inputs, they provide setup times as low as 1.1 ns and
hold times of 0 ns. As outputs, these registers provide clock-to-output
13
times as low as 2.5 ns. IOEs provide a variety of features, such as JTAG
BST support, slew-rate control, tri-state buffers, and open-drain outputs.
Figure 1
shows a block diagram of the ACEX 1K device architecture. Each
group of LEs is combined into an LAB; groups of LABs are arranged into
rows and columns. Each row also contains a single EAB. The LABs and
EABs are interconnected by the FastTrack Interconnect routing structure.
IOEs are located at the end of each row and column of the FastTrack
Interconnect routing structure.
Altera Corporation
7