EPF10K30ATI144-3 Altera, EPF10K30ATI144-3 Datasheet - Page 29
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EPF10K30ATI144-3
Manufacturer Part Number
EPF10K30ATI144-3
Description
IC FLEX 10KA FPGA 30K 144-TQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K30ATI144-3
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
12288
Number Of I /o
102
Number Of Gates
69000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Family Name
FLEX 10KA
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# Registers
738
# I/os (max)
102
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
3.3V
Logic Cells
1728
Ram Bits
12288
Device System Gates
69000
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1265
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K30ATI144-3
Manufacturer:
FUJITSU
Quantity:
2 000
Part Number:
EPF10K30ATI144-3
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EPF10K30ATI144-3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
I/O Element
An I/O element (IOE) contains a bidirectional I/O buffer and a register
that can be used either as an input register for external data that requires
a fast setup time, or as an output register for data that requires fast clock-
to-output performance. In some cases, using an LE register for an input
register will result in a faster setup time than using an IOE register. IOEs
can be used as input, output, or bidirectional pins. For bidirectional
registered I/O implementation, the output register should be in the IOE
and, the data input and output enable register should be LE registers
placed adjacent to the bidirectional pin. The Compiler uses the
programmable inversion option to invert signals from the row and
column interconnect automatically where appropriate.
Figure 13
shows
the bidirectional I/O registers.
Altera Corporation
29