EP2C35F672I8N Altera, EP2C35F672I8N Datasheet - Page 102
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EP2C35F672I8N
Manufacturer Part Number
EP2C35F672I8N
Description
IC CYCLONE II FPGA 33K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F672I8N
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
475
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
33216
# I/os (max)
475
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
33216
Ram Bits
483840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
For Use With
P0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2111
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C35F672I8N
Manufacturer:
INFINEON
Quantity:
200
Company:
Part Number:
EP2C35F672I8N
Manufacturer:
ALTERA42
Quantity:
201
Part Number:
EP2C35F672I8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
DC Characteristics for Different Pin Types
5–12
Cyclone II Device Handbook, Volume 1
Notes to
(1)
(2)
Note to
(1)
Bus-hold low, sustaining
current
Bus-hold high, sustaining
current
Bus-hold low, overdrive
current
Bus-hold high, overdrive
current
Bus-hold trip point
25-Ω R
50-Ω R
50-Ω R
Table 5–11. Bus Hold Parameters
Table 5–12. Series On-Chip Termination Specifications
Symbol
There is no specification for bus-hold at V
The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
For commercial –8 devices, the tolerance is ±40%.
S
S
S
Table
Parameter
Table
Internal series termination without
calibration (25-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
5–12:
5–11:
(2)
Description
Table 5–11
On-Chip Termination Specifications
Table 5–12
tolerance when using series or differential on-chip termination.
V
V
V
V
0 V < V
0 V < V
I N
I L
I N
I L
(maximum)
(minimum)
Conditions
>
<
I N
I N
—
Note (1)
< V
< V
specifies the bus hold parameters for general I/O pins.
defines the specifications for internal termination resistance
CCIO
C C I O
C C I O
V
V
V
= 1.5 V for the HSTL I/O standard.
C C I O
C C I O
C C I O
Conditions
0.68
Min
–30
30
—
—
= 3.3V
= 2.5V
= 1.8V
1.8 V
–200
Max
1.07
200
—
—
Commercial
±30
Max
±30
±30
Min
–50
0.7
(1)
50
V
—
—
CCIO
2.5 V
Resistance Tolerance
Level
Industrial
–300
Max
300
1.7
—
—
Max
±30
±30
±40
Min
–70
0.8
70
—
—
Automotive
Temp Max
Altera Corporation
Extended/
3.3 V
±40
±40
±50
February 2008
–500
Max
500
2.0
—
—
Unit
Unit
μA
μA
μA
μA
%
%
%
V