EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 7
![IC CYCLONE III FPGA 55K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C55F484C8N
Manufacturer Part Number
EP3C55F484C8N
Description
IC CYCLONE III FPGA 55K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C55F484C8N.pdf
(274 pages)
Specifications of EP3C55F484C8N
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2396160
Number Of I /o
327
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
55856
# I/os (max)
327
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
55856
Ram Bits
2396160
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
3491
Family Type
Cyclone III
No. Of I/o's
327
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2510
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C55F484C8N
Manufacturer:
ALTERA
Quantity:
490
Part Number:
EP3C55F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 1: Cyclone III Device Data Sheet
Electrical Characteristics
Table 1–5. Cyclone III Devices Bus Hold Parameter
© January 2010 Altera Corporation
Bus-hold
low,
sustaining
current
Bus-hold
high,
sustaining
current
Bus-hold
low,
overdrive
current
Bus-hold
high,
overdrive
current
Bus-hold trip
point
Note to
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Parameter
Table
1–5:
V
(maximum)
V
(minimum)
0 V < V
0 V < V
IN
IN
Condition
> V
< V
IL
IL
—
IN
IN
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 1–5
OCT Specifications
Table 1–6
and voltage.
Table 1–6. Cyclone III Devices Series OCT without Calibration Specifications
OCT calibration is automatically performed at device power-up for OCT enabled
I/Os.
Series OCT without
calibration
< V
< V
CC IO
CC IO
Description
Min
0.3
lists bus hold specifications for Cyclone III devices.
lists the variation of OCT without calibration across process, temperature,
–8
—
—
8
1.2
–125
Max
125
0.9
—
—
0.375 1.125 0.68
Min
–12
12
—
—
V
CCIO
1.5
3.0
2.5
1.8
1.5
1.2
(Note 1)
–175
(V)
Max
175
—
—
Min
–30
30
—
—
Commercial
1.8
Max
±30
±30
+40
+50
+50
–200
Max
1.07
200
V
—
—
CC IO
Resistance Tolerance
(V)
Min
–50
0.7
50
—
—
2.5
Industrial and Automotive
–300
Max
300
1.7
—
—
Cyclone III Device Handbook, Volume 2
Min
–70
0.8
70
—
—
Max
±40
±40
±50
±50
±50
3.0
–500
Max
500
—
—
2
Min
–70
0.8
70
—
—
3.3
–500
Max
500
—
—
2
Unit
%
%
%
%
%
1–7
Unit
μA
μA
μA
μA
V