EP1S10F780C7 Altera, EP1S10F780C7 Datasheet - Page 128
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EP1S10F780C7
Manufacturer Part Number
EP1S10F780C7
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F780C7
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
426
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1112
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F780C7
Manufacturer:
EUTECH
Quantity:
3 930
Company:
Part Number:
EP1S10F780C7ES
Manufacturer:
ALTERA
Quantity:
44
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Part Number:
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Part Number:
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Manufacturer:
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Company:
Part Number:
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Quantity:
3 000
Part Number:
EP1S10F780C7N
Manufacturer:
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Quantity:
20 000
I/O Structure
Figure 2–67. Stratix IOE in DDR Output I/O Configuration
Notes to
(1)
(2)
2–114
Stratix Device Handbook, Volume 1
Column or Row
Interconnect
All input signals to the IOE can be inverted at the IOE.
The tristate is by default active high. It can, however, be designed to be active low.
I/O Interconnect
Figure
[15..0]
IOE_CLK[7..0]
2–67:
clkout
aclr/prn
sclr
Chip-Wide Reset
Register Delay
Register Delay
Logic Array
Enable Clock
Enable Delay
Enable Delay
Logic Array
Output Clock
to Output
to Output
Output
Output Register
Output Register
OE Register
OE Register
ENA
Notes
D
CLRN/PRN
D
CLRN/PRN
D
CLRN/PRN
D
CLRN/PRN
ENA
ENA
ENA
Q
Q
Q
Q
(1),
(2)
Drive Strength Control
Used for
DDR SDRAM
Pin Delay
Output
Open-Drain Output
Slew Control
clk
t
ZX
Output
Delay
OE Register
t
CO
Delay
V
CCIO
Altera Corporation
V
CCIO
Optional
PCI Clamp
Bus-Hold
Circuit
Programmable
Pull-Up
Resistor
July 2005