EP2C50F672C6N Altera, EP2C50F672C6N Datasheet - Page 35
![IC CYCLONE II FPGA 50K 672-FBGA](/photos/6/72/67289/ep2c50f672c6n_sml.jpg)
EP2C50F672C6N
Manufacturer Part Number
EP2C50F672C6N
Description
IC CYCLONE II FPGA 50K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C50F672C6N
Number Of Logic Elements/cells
50528
Number Of Labs/clbs
3158
Total Ram Bits
594432
Number Of I /o
450
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2125
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C50F672C6N
Manufacturer:
ALTERA
Quantity:
745
Part Number:
EP2C50F672C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–14. Global Clock Network Multiplexers
Altera Corporation
February 2007
Global Clock
Network
Clock [15 or 7..0]
Global Clock Network Distribution
Cyclone II devices contains 16 global clock networks. The device uses
multiplexers with these clocks to form six-bit buses to drive column IOE
clocks, LAB row clocks, or row IOE clocks (see
multiplexer at the LAB level selects two of the six LAB row clocks to feed
the LE registers within the LAB.
LAB row clocks can feed LEs, M4K memory blocks, and embedded
multipliers. The LAB row clocks also extend to the row I/O clock regions.
IOE clocks are associated with row or column block regions. Only six
global clock resources feed to these row and column regions.
shows the I/O clock regions.
Cyclone II Device Handbook, Volume 1
Column I/O Region
IO_CLK [5..0]
LAB Row Clock
LABCLK[5..0]
Row I/O Region
IO_CLK [5..0]
Figure
Cyclone II Architecture
2–14). Another
Figure 2–15
2–23
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