EP2C70F672C6N Altera, EP2C70F672C6N Datasheet - Page 145

• Manufacturer Part Number: EP2C70F672C6N
• Description: IC CYCLONE II FPGA 70K 672-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C70F672C6N

• Number Of Logic Elements/cells: 68416
• Number Of Labs/clbs: 4276
• Total Ram Bits: 1152000
• Number Of I /o: 422
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• For Use With: P0304 - DE2-70 CALL FOR ACADEMIC PRICING544-1703 - VIDEO KIT W/CYCLONE II EP2C70N544-1699 - DSP KIT W/CYCLONE II EPS2C70N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2141

Altera Corporation
February 2008
SSTL_2_CLASS_I
SSTL_18_CLASS_I
High-speed clock
Duty cycle
High-speed I/O data rate
Time unit interval
Channel-to-channel skew
Table 5–46. Maximum Output Clock Toggle Rate Derating Factors (Part 4 of 4)
Table 5–47. High-Speed I/O Timing Definitions (Part 1 of 2)
I/O Standard
Parameter
OCT_50
_OHMS
OCT_50
_OHMS
Strength
f
t
HSIODR High-speed receiver and transmitter input and output data rate.
TUI
TCCS
H S C K L K
D U T Y
Symbol
Drive
High Speed I/O Timing Specifications
The timing analysis for LVDS, mini-LVDS, and RSDS is different
compared to other I/O standards because the data communication is
source-synchronous.
You should also consider board skew, cable skew, and clock jitter in your
calculation. This section provides details on the timing parameters for
high-speed I/O standards in Cyclone II devices.
Table 5–47
Figure
5–3.
Speed
Grade
High-speed receiver and transmitter input and output clock frequency.
Duty cycle on high-speed transmitter output clock.
TUI = 1/HSIODR.
The timing difference between the fastest and slowest output edges,
including t
TCCS measurement.
TCCS = TUI – SW – (2 × RSKM)
–6
67
30
Column I/O Pins
defines the parameters of the timing diagram shown in
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
Speed
Grade
–7
69
33
CO
variation and clock skew. The clock is included in the
Speed
Grade
–8
70
36
DC Characteristics and Timing Specifications
Speed
Grade
–6
25
47
Row I/O Pins
Description
Cyclone II Device Handbook, Volume 1
Speed
Grade
–7
42
49
Speed
Grade
–8
60
51
Speed
Grade
–6
25
47
Dedicated Clock
Outputs
Speed
Grade
–7
42
49
Speed
Grade
5–55
–8
60
51