EP2S60F672C5N Altera, EP2S60F672C5N Datasheet - Page 117
![IC STRATIX II FPGA 60K 672-FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP2S60F672C5N
Manufacturer Part Number
EP2S60F672C5N
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C5N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
492
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1914
EP2S60F672C5N
EP2S60F672C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F672C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 117 of 238
- Download datasheet (3Mb)
Altera Corporation
May 2007
Notes to
(1)
(2)
Table 3–3. 32-Bit Stratix II Device IDCODE
EP2S130
EP2S180
EP2S15
EP2S30
EP2S60
EP2S90
Device
The most significant bit (MSB) is on the left.
The IDCODE's least significant bit (LSB) is always 1.
Table
3–3:
Version
(4 Bits)
0000
0000
0001
0000
0000
0000
The Quartus II software has an Auto Usercode feature where you can
choose to use the checksum value of a programming file as the JTAG user
code. If selected, the checksum is automatically loaded to the USERCODE
register. Turn on the Auto Usercode option by clicking Device & Pin
Options, then General, in the Settings dialog box (Assignments menu).
1
Table 3–2. Stratix II Boundary-Scan Register Length
0010 0000 1001 0001
0010 0000 1001 0010
0010 0000 1001 0011
0010 0000 1001 0100
0010 0000 1001 0101
0010 0000 1001 0110
Part Number (16 Bits)
Stratix, Stratix II, Cyclone, and Cyclone II devices must be
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix, Stratix II,
Cyclone, and Cyclone II devices are in the 18th or after they fail
configuration. This does not affect SignalTap II.
EP2S130
EP2S180
EP2S15
EP2S30
EP2S60
EP2S90
Device
IDCODE (32 Bits)
Manufacturer Identity (11
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
(1)
Stratix II Device Handbook, Volume 1
Boundary-Scan Register Length
Bits)
Configuration & Testing
1,140
1,692
2,196
2,748
3,420
3,948
LSB (1 Bit)
1
1
1
1
1
1
(2)
3–3
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