XC3S50AN-4TQG144C Xilinx Inc, XC3S50AN-4TQG144C Datasheet - Page 37
![IC SPARTAN-3AN FPGA 50K 144TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC3S50AN-4TQG144C
Manufacturer Part Number
XC3S50AN-4TQG144C
Description
IC SPARTAN-3AN FPGA 50K 144TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3S50AN-4TQG144C.pdf
(2 pages)
3.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S50AN-4TQG144C
Total Ram Bits
55296
Number Of Logic Elements/cells
1584
Number Of Labs/clbs
176
Number Of I /o
108
Number Of Gates
50000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
No. Of Logic Blocks
1584
No. Of Gates
50000
No. Of Macrocells
1584
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
108
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1555
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S50AN-4TQG144C
Manufacturer:
TOSHIBA
Quantity:
1 000
Company:
Part Number:
XC3S50AN-4TQG144C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S50AN-4TQG144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Three-State Output Propagation Times
Table 28: Timing for the IOB Three-State Path
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
Synchronous Output Enable/Disable Times
T
T
Asynchronous Output Enable/Disable Times
T
Set/Reset Times
T
T
IOCKHZ
IOCKON
GTS
IOSRHZ
IOSRON
Symbol
The numbers in this table are tested using the methodology presented in
Table 10
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from
(2)
(2)
and
Time from the active transition at the OTCLK
input of the Three-state Flip-Flop (TFF) to when
the Output pin enters the high-impedance state
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
Time from asserting the Global Three State
(GTS) input on the STARTUP_SPARTAN3A
primitive to when the Output pin enters the
high-impedance state
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
Table
13.
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
LVCMOS25, 12 mA
output drive, Fast slew
rate
LVCMOS25, 12 mA
output drive, Fast slew
rate
LVCMOS25, 12 mA
output drive, Fast slew
rate
Conditions
Table 30
Table
29.
and are based on the operating conditions set forth in
Device
All
All
All
All
All
Speed Grade
Max
0.63
2.80
9.47
1.61
3.57
-5
10.36
Max
0.76
3.06
1.86
3.82
-4
Units
ns
ns
ns
ns
ns
37