XC4VFX12-10FFG668C Xilinx Inc, XC4VFX12-10FFG668C Datasheet
XC4VFX12-10FFG668C
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XC4VFX12-10FFG668C
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XC4VFX12-10FFG668C Summary of contents
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DS302 (v3.7) September 9, 2009 Virtex-4 FPGA Electrical Characteristics Virtex®-4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance. Virtex-4 FPGA DC and AC characteristics are specified for both commercial and industrial grades. ...
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Table 1: Absolute Maximum Ratings (Continued) Symbol Voltage applied to 3-state 3.3V output (all user and dedicated I/Os) Voltage applied to 3-state 3.3V output V TS (restricted to maximum of 100 user I/Os) 2.5V or below I/O input voltage relative ...
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Table 2: Recommended Operating Conditions (Continued) Symbol (6) AVCCAUXRX Auxiliary receive supply voltage relative to GNDA (6) AVCCAUXTX Auxiliary transmit supply voltage relative to GNDA AVCCAUXMGT Auxiliary management supply voltage relative to GNDA (7) V Terminal receive supply voltage relative ...
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... Note (6) XC4VLX60 167 Note (6) XC4VLX80 220 Note (6) XC4VLX100 292 Note (6) XC4VLX160 384 Note (6) XC4VLX200 489 Note (6) XC4VSX25 94 Note (6) XC4VSX35 140 Note (6) XC4VSX55 271 Note (6) XC4VFX12 47 Note (6) XC4VFX20 71 Note (6) XC4VFX40 139 Note (6) XC4VFX60 203 Note (6) XC4VFX100 311 Note (6) XC4VFX140 442 Note (6) Units ...
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... Note (6) XC4VLX40 43 Note (6) XC4VLX60 74 Note (6) XC4VLX80 83 Note (6) XC4VLX100 95 Note (6) XC4VLX160 133 Note (6) XC4VLX200 150 Note (6) XC4VSX25 62 Note (6) XC4VSX35 70 Note (6) XC4VSX55 91 Note (6) XC4VFX12 31 Note (6) XC4VFX20 35 Note (6) XC4VFX40 69 Note (6) XC4VFX60 80 Note (6) XC4VFX100 98 Note (6) XC4VFX140 143 Note (6) XC4VFX20 25 154 XC4VFX60 35 154 XC4VFX100 50 154 Units ...
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Table 4: Quiescent Supply Current (Continued) Symbol (4) I Quiescent AVCCAUXTX supply current CCAUXTX (4,5) I Quiescent V supply current TTX TTX (4,5) I Quiescent V supply current TRX TRX (4) Quiescent V I AUXMGT AUXMGT Notes: 1. Typical values ...
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... XC4VLX60 300 XC4VLX80 400 XC4VLX100 500 XC4VLX160 700 XC4VLX200 850 XC4VSX25 175 XC4VSX35 250 XC4VSX55 400 XC4VFX12 111 XC4VFX20 151 XC4VFX40 244 XC4VFX60 339 XC4VFX100 511 XC4VFX140 702 Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. Maximum values are specified under worst-case process, voltage, and temperature conditions. ...
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SelectIO™ DC Input and Output Levels Values for V and V are recommended input voltages Values for I and I are guaranteed over the recom mended operating conditions at the V points. Only selected standards are ...
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LDT DC Specifications (LDT_25) Table 8: LDT DC Specifications Symbol DC Parameter V Supply Voltage CCO V Differential Output Voltage OD Δ V Change in V Magnitude Output Common Mode Voltage OCM Δ V Change in V ...
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Extended LVDS DC Specifications (LVDSEXT_25) Table 10: Extended LVDS DC Specifications Symbol DC Parameter V Supply Voltage CCO V Output High Voltage for Q and Output Low Voltage for Q and Q OL Differential Output Voltage (Q ...
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RocketIO DC Input and Output Levels Table 12 summarizes the DC input and output specifica- tions of the Virtex-4 FPGA RocketIO Multi-Gigabit Serial Transceivers. Figure 1 shows the single-ended output volt- Table 12: RocketIO DC Specifications DC Parameter Peak-to-Peak Differential ...
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... Mb/s Table 14: Virtex-4 Device Speed Grade Designations Device Advance XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 www.xilinx.com Speed Grade -11 -10 710 MHz 645 MHz 1 Gb/s 800 Mb/s 533 Mb/s 500 Mb/s ...
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Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Testing of Switching Characteristics All devices are 100% functionally tested. Internal timing ...
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Table 16: Processor Block Switching Characteristics Description Setup and Hold Relative to Clock (CPMC405CLOCK) Clock and Power Management control inputs Reset control inputs Debug control inputs Trace control inputs External Interrupt Controller control inputs Clock to Out Clock and Power ...
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Table 19: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics Description Setup and Hold Relative to Clock (BRAMDSOCMCLK) Data-Side On-Chip Memory data bus inputs Clock to Out Data-Side On-Chip Memory control outputs Data-Side On-Chip Memory address bus outputs T Data-Side On-Chip ...
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Table 22: Processor Block APU Interface Switching Characteristics Description Setup and Hold Relative to Clock (CPMDFCMCLOCK) APU bus control inputs APU bus data inputs Clock to Out APU bus control outputs APU bus data outputs RocketIO Switching Characteristics Consult the ...
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Table 25: RocketIO Receiver Switching Characteristics Description Serial data rate, -10 Serial data rate, -11 XAUI Receive Jitter Tolerance (8B/10B CJPAT) Receive Deterministic Jitter Tolerance Receive Total Jitter Tolerance Receive Sinusoidal Jitter Tolerance General Receive Jitter Tolerance Receive deterministic jitter ...
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Table 26: RocketIO Transmitter Switching Characteristics Description Serial data rate, -10 Serial data rate, -11 (3) TX Jitter Generation (2) TX rise time (2) TX fall time TXUSRCLK frequency TXUSRCLK2 frequency TXUSRCLK duty cycle TXUSRCLK2 duty cycle Differential output skew ...
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IOB Pad Input/Output/3-State Switching Characteristics Table 27 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard and 3-state delays described as the delay from IOB pad through the IOPI input ...
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Table 27: IOB Switching Characteristics IOSTANDARD (1) Attribute -12 LVTTL, Slow 0.76 LVTTL, Slow 0.76 LVTTL, Slow 0.76 LVTTL, Fast 0.76 LVTTL, Fast 0.76 LVTTL, Fast 0.76 LVTTL, ...
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Table 27: IOB Switching Characteristics IOSTANDARD (1) Attribute -12 LVCMOS25, Fast 0.69 LVCMOS25, Fast 0.69 LVCMOS18, Slow 0.97 LVCMOS18, Slow 0.97 LVCMOS18, Slow 0.97 LVCMOS18, Slow 0.97 LVCMOS18, ...
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Table 27: IOB Switching Characteristics IOSTANDARD (1) Attribute -12 (3) HSTL_II_DCI 1.28 (3) HSTL_III_DCI 1.28 (3) HSTL_IV_DCI 1.28 (3) HSTL_I_DCI_18 1.26 (3) HSTL_II_DCI_18 1.26 (3) HSTL_III_DCI_18 1.26 (3) HSTL_IV_DCI_18 1.26 (3) SSTL2_I_DCI 1.31 (3) SSTL2_II_DCI 1.31 LVPECL_25 1.38 SSTL18_I 1.31 ...
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I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 30 shows the test setup parameters used for measuring input delay. Table 30: Input Delay Measurement Methodology Description LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, ...
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Output Delay Measurements Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4 inches of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4 inch trace is ...
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Table 31: Output Delay Measurement Methodology (Continued) Description HSTL, Class IV, 1.8V SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, Class II, 2.5V LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended ...
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Input/Output Logic Switching Characteristics Table 32: ILOGIC Switching Characteristics Symbol Setup/Hold / T T CE1 pin Setup/Hold with respect to CLK ICE1CK ICKCE1 / T T DLYCE pin Setup/Hold with respect to C ICECK ICKCE / T T DLYRST pin ...
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Table 33: OLOGIC Switching Characteristics Symbol Setup/Hold / T T D1/D2 pins Setup/Hold with respect to CLK ODCK OCKD / T T OCE pin Setup/Hold with respect to CLK OOCECK OCKOCE / T T SR/REV pin Setup/Hold with respect to ...
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Input Serializer/Deserializer Switching Characteristics Table 34: ISERDES Switching Characteristics Symbol Setup/Hold for Control Lines / T T ISCCK_BITSLIP ISCKC_BITSLIP ( ISCCK_CE ISCKC_CE ( ISCCK_CE2 ISCKC_CE2 / T T ISCCK_DLYCE ISCKC_DLYCE / T T ISCCK_DLYINC ...
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Input Delay Switching Characteristics Table 35: Input Delay Switching Characteristics Symbol IDELAYCTRL Reset to Ready for IDELAYCTRL T IDELAYCTRLCO_RDY (Maximum) F REFCLK frequency IDELAYCTRL_REF (2) REFCLK precision IDELAYCTRL_REF_PRECISION T Minimum Reset pulse width IDELAYCTRL_RPW IDELAY T IDELAY Chain Delay Resolution ...
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Output Serializer/Deserializer Switching Characteristics Table 36: OSERDES Switching Characteristics Symbol Setup/Hold / input Setup/Hold with respect to CLKDIV OSDCK_D OSCKD_D ( input Setup/Hold with respect to CLK OSDCK_T OSCKD_T ( ...
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... A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed, there is no positive hold time. 2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent 4VLX/SX -12 column. 3. ...
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... A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed, there is no positive hold time. 2. The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent XC4VLX/SX -12 column. 3. ...
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Block RAM and FIFO Switching Characteristics Table 40: Block RAM Switching Characteristics Symbol Sequential Delays Clock CLK to DOUT output (without output register) T Clock CLK to DOUT output with ECC RCKO_DORA (without output register) Clock CLK to DOUT output ...
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Table 41: FIFO Switching Characteristics Symbol Sequential Delays T Clock CLK to DO output FCKO_DO T Clock CLK to FIFO flags outputs FCKO_FLAGS T Clock CLK to FIFO pointer outputs FCKO_POINTERS Setup and Hold Times Before Clock CLK / T ...
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XtremeDSP™ Switching Characteristics Table 42: XtremeDSP Switching Characteristics Symbol Setup and Hold of CE Pins / T T Setup/Hold of all CE inputs of the DSP48 slice DSPCCK_CE DSPCKC_CE / T T Setup/Hold of all RST inputs of the DSP48 ...
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Configuration Switching Characteristics Table 43: Configuration Switching Characteristics Symbol Power-up Timing Characteristics (1,2) T CONFIG POR T ICCK T PROGRAM Master/Slave Serial Mode Programming Switching / T T DCC CCD / T T DSCK SCKD T CCO ...
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Table 43: Configuration Switching Characteristics (Continued) Symbol Boundary-Scan Port Timing Specifications T TAPTCK T TCKTAP T TCKTDO F TCK F TCKB Dynamic Reconfiguration Port (DRP) for DCM CLKIN_FREQ_DLL_HF_MS_MAX T /T DMCCK_DADDR DMCKC_DADDR T /T DMCCK_DI DMCKC_DI T /T DMCCK_DEN DMCKC_DEN ...
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Clock Buffers and Networks Table 44: Global Clock Switching Characteristics (Including BUFGCTRL) Symbol ( pins Setup/Hold BCCCK_CE BCCKC_CE ( pins Setup/Hold BCCCK_S BCCKC_S T BUFGCTRL delay BCCKO_O Maximum Frequency F Global clock ...
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Table 45: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode (Continued) Symbol CLKOUT_FREQ_FX_HF_MS_MIN CLKOUT_FREQ_FX_HF_MS_MAX Input Clocks (High Frequency Mode) (6) CLKIN_FREQ_DLL_HF_MS_MIN CLKIN_FREQ_DLL_HF_MS_MAX CLKIN_FREQ_FX_HF_MS_MIN (6) CLKIN_FREQ_FX_HF_MS_MAX PSCLK_FREQ_HF_MS_MIN PSCLK_FREQ_HF_MS_MAX Notes: 1. DLL outputs are used in these instances to describe ...
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Table 47: Input Clock Tolerances Symbol Duty Cycle Input Tolerance (in %) CLKIN_PSCLK_PULSE_RANGE_1 CLKIN_PSCLK_PULSE_RANGE_1_50 CLKIN_PSCLK_PULSE_RANGE_50_100 CLKIN_PSCLK_PULSE_RANGE_100_200 CLKIN_PSCLK_PULSE_RANGE_200_400 CLKIN_PSCLK_PULSE_RANGE_400 Input Clock Cycle-Cycle Jitter (Low Frequency Mode) CLKIN_CYC_JITT_DLL_LF CLKIN_CYC_JITT_FX_LF Input Clock Cycle-Cycle Jitter (High Frequency Mode) CLKIN_CYC_JITT_DLL_HF CLKIN_CYC_JITT_FX_HF Input Clock Period Jitter ...
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Output Clock Jitter Table 48: Output Clock Jitter Description Clock Synthesis Period Jitter CLK0 CLK90 CLK180 CLK270 CLK2X, CLK2X180 CLKDV (integer division) CLKDV (non-integer division) CLKFX, CLKFX180 Notes: 1. PMCD outputs are not included in this table because they do ...
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Table 50: Miscellaneous Timing Parameters Symbol Time Required to Achieve LOCK T_LOCK_DLL_240 T_LOCK_DLL_120_240 T_LOCK_DLL_60_120 T_LOCK_DLL_50_60 T_LOCK_DLL_40_50 T_LOCK_DLL_30_40 T_LOCK_DLL_24_30 T_LOCK_DLL_30 T_LOCK_FX_MAX T_LOCK_DLL_FINE_SHIFT Fine Phase Shifting FINE_SHIFT_RANGE_MS FINE_SHIFT_RANGE_MR Delay Lines DCM_TAP_MS_MIN DCM_TAP_MS_MAX DCM_TAP_MR_MIN DCM_TAP_MR_MAX Input Signal Requirements (4) DCM_RESET DCM_INPUT_CLOCK_STOP Notes: 1. ...
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Table 51: Frequency Synthesis Attribute CLKFX_MULTIPLY CLKFX_DIVIDE Table 52: DCM Switching Characteristics Symbol / T T DMCCK_PSEN DMCKC_PSEN / T T DMCCK_PSINCDEC DMCKC_PSINCDEC T DMCKO_PSDONE Table 53: PMCD Switching Characteristic Symbol / T T PMCCCK_REL PMCCKC_REL T PMCCO_CLK{A1,B,C,D} T PMCCKO_CLK{A1,B,C,D} ...
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... DCM output jitter is already included in the timing calculation. DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 www.xilinx.com Speed Grade Device -12 -11 -10 2.43 2.81 3.25 2.60 2 ...
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... IOB and CLB flip-flops are clocked by the global clock net. DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 www.xilinx.com Speed Grade Device -12 -11 -10 6.42 7.22 8.14 6.50 7 ...
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... DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) with DCM XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 www.xilinx.com Speed Grade Units -12 -11 -10 (1) 1.35 1.52 1.54 ns –0.72 – ...
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... Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description (1,2) , page 19. (2) with DCM in XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 www.xilinx.com Speed Grade Device 12 11 – – – (1) Using DCM and Global Clock Buffer. For –0.33 –0.33 – ...
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... DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description XC4VLX15 (2) without DCM XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 www.xilinx.com Speed Grade Device -12 -11 -10 (1) 1.82 2.33 2.74 0.11 ...
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... DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description Device (1) (2) XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 www.xilinx.com Speed Grade -12 -11 -10 All 150 150 150 ...
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... DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description Device (1) XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 www.xilinx.com Package Value Units SF363 80 ps FF668 120 ps SF363 ...
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... Device (1) (2) Description Table 63: JTAG ID Code by Step Device XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 Notes: 1. Shaded cells represent devices not produced at that stepping. www.xilinx.com Speed Grade -12 -11 -10 All 450 500 ...
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Current Virtex-4 Production Devices Table 64 summarizes the current production LX and SX device stepping. Table 64: Current LX and SX Production Devices LX/SX Device Stepping Example Ordering Code Device steppings shipped when ordered per Example Ordering Code (1) Capability ...
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Revision History The following table shows the revision history for this document. Date Version 08/02/04 1.0 Initial Xilinx release. Printed Handbook version. 09/09/04 1.1 Edits in Tables 12, 13, 18, 19, 20, 22, 26, 28, 37, and 38. Removed Table ...
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Date Version 02/03/06 1.11 Revised the speed specification requirements in parameter changes in and I Table Table 600 mV and added a new Note 1. Also in specification from 95mV to 950mV. Changed performance numbers in the typical specification for ...
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... SPEED SPECIFICATION version for this data sheet release: v1.62. Table 1: Removed former note Table 14: Moved XC4VFX12-11, XC4VFX20-11, XC4VFX60-11, and XC4VFX100-11 devices to Production status. Table 15: Expanded to break out processor clock specifications into Characteristics when APU Not Used and Characteristics when APU Used. Removed specs for CPMFCMCLK, not available ...
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... Added Notes (4) through (7) to these parameters. Table 60: Removed FF1760 package. Not supported. Table 63: Added FX devices and JTAG IDs. SPEED SPECIFICATION version for this data sheet release: v1.65. Table 14: Promoted -12 speed grade devices of XC4VFX12, XC4VFX20, and XC4VFX60 to Production status. Table 37: Removed parameter T ISCCK_REV be connected to GND. Table ...
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Date Version 09/28/07 3.0 • • • • • • 12/11/07 3.1 • • • • • • • • • • • 04/10/08 3.2 • • • • 06/06/08 3.3 • • • • 11/26/08 3.4 • 06/16/09 3.5 ...
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Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY ...