XC5VLX30-1FFG676C Xilinx Inc, XC5VLX30-1FFG676C Datasheet - Page 110
![IC FPGA VIRTEX-5 30K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-1FFG676C
Manufacturer Part Number
XC5VLX30-1FFG676C
Description
IC FPGA VIRTEX-5 30K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-1FFG676C
Total Ram Bits
1179648
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Number Of I /o
400
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
No. Of Logic Blocks
4800
No. Of Gates
30000
Family Type
Virtex-5 LX
No. Of Speed Grades
1
No. Of I/o's
400
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1559
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Chapter 3: Phase-Locked Loops (PLLs)
110
PLL Application Example
The following PLL attribute settings result in a wide variety of synthesized clocks:
Figure 3-16
X-Ref Target - Figure 3-16
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
VCOCLK
REFCLK
CLKOUT0_PHASE = 0;
CLKOUT0_DUTY_CYCLE = 0.5;
CLKOUT0_DIVIDE = 2;
CLKOUT1_PHASE = 90;
CLKOUT1_DUTY_CYCLE = 0.5;
CLKOUT1_DIVIDE = 2;
CLKOUT2_PHASE = 0;
CLKOUT2_DUTY_CYCLE = 0.25;
CLKOUT2_DIVIDE = 4;
CLKOUT3_PHASE = 90;
CLKOUT3_DUTY_CYCLE = 0.5;
CLKOUT3_DIVIDE = 8;
CLKOUT4_PHASE = 0;
CLKOUT4_DUTY_CYCLE = 0.5;
CLKOUT4_DIVIDE = 8;
CLKOUT5_PHASE = 135;
CLKOUT5_DUTY_CYCLE = 0.5;
CLKOUT5_DIVIDE = 8;
CLKFBOUT_PHASE = 0;
CLKFBOUT_MULT = 8;
DIVCLK_DIVIDE = 1;
CLKIN1_PERIOD = 10.0;
displays the resulting waveforms.
www.xilinx.com
Figure 3-16: Example Waveform
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_3_19_032506
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