XC5VLX50-1FFG1153C Xilinx Inc, XC5VLX50-1FFG1153C Datasheet - Page 67
![IC FPGA VIRTEX-5 50K 1153FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-1FFG1153C
Manufacturer Part Number
XC5VLX50-1FFG1153C
Description
IC FPGA VIRTEX-5 50K 1153FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FFG1153C
Total Ram Bits
1769472
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
560
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1153-BBGA, FCBGA
No. Of Logic Blocks
3600
No. Of Macrocells
50000
Family Type
Virtex-5
No. Of Speed Grades
1
No. Of I/o's
560
Clock Management
DCM, PLL
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1561
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50-1FFG1153C
Manufacturer:
ISSI
Quantity:
15
Company:
Part Number:
XC5VLX50-1FFG1153C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC5VLX50-1FFG1153CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 89: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL
in System-Synchronous Mode
T
ICKOFDCM_PLL
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
DCM and PLL output jitter are already included in the timing calculation.
Symbol
Global Clock and OUTFF with DCM and PLL
Description
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
XC5VLX20T
XC5VLX30
XC5VLX30T
XC5VLX50
XC5VLX50T
XC5VLX85
XC5VLX85T
XC5VLX110
XC5VLX110T
XC5VLX155
XC5VLX155T
XC5VLX220
XC5VLX220T
XC5VLX330
XC5VLX330T
XC5VSX35T
XC5VSX50T
XC5VSX95T
XC5VSX240T
XC5VTX150T
XC5VTX240T
XC5VFX30T
XC5VFX70T
XC5VFX100T
XC5VFX130T
XC5VFX200T
Device
2.38
2.43
2.47
2.40
2.25
2.25
2.27
2.27
2.33
2.33
2.38
2.43
2.36
2.38
2.25
2.32
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-3
Speed Grade
2.45
2.48
2.48
2.50
2.50
2.55
2.55
2.61
2.61
2.66
2.66
2.75
2.75
2.92
2.92
2.59
2.61
2.56
2.92
2.69
2.70
2.74
2.66
2.51
2.59
2.79
-2
2.84
2.84
2.84
2.86
2.86
2.91
2.91
2.97
2.97
3.01
3.01
3.09
3.09
3.28
3.28
2.94
2.96
2.91
3.27
3.06
3.06
3.11
3.03
2.91
2.98
3.18
-1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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