EP3C5F256C6 Altera, EP3C5F256C6 Datasheet - Page 64

• Manufacturer Part Number: EP3C5F256C6
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C6

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-2418; EP3C5F256C6

Page 64
“Verification” on page 45
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Done
N/A
Use the
configuration.
Use the auto-restart configuration after error option to force the Cyclone III device
reconfiguration if there is any error during configuration.
Use compressed configuration file for configuring the Cyclone III device to reduce storage
requirement and configuration time.
Use the RBF file to estimate the amount of storage space required for configuration data.
Perform I/O assignment analysis with the Quartus II software. The Quartus II software also
checks the location of I/O pads for any restrictions.
Do not sink or source current through the I/O pins above the recommended specification.
You can also set the limit in the Quartus II software.
Use the TimeQuest Timing Analyzer to perform timing analysis. Specify the frequencies and
relationships for all clocks in your design. Use input and output delay constraints to specify
external device or board timing parameters.
Perform the Early Timing Estimation if you need a timing estimation before running a full
compilation.
Check the timing report and make sure there is no t
Use the Quartus II assignment to specify the input and output delay.
Use the Quartus II assignment to specify the data and clock skew.
Use the physical synthesis option or the Design Space Explorer utility to optimize the
fitting for performance or area.
Perform recovery and removal timing analysis for asynchronous control signals
Use the
Use the Optimization Advisors as guidance to make settings to optimize your design on
resources or timing.
Turn on the Optimize fast-corner timing option to increase the timing robustness of your
design.
Check the Analysis & Synthesis section on the compilation report to ensure that the
registers are not removed unintentionally.
Turn on Optimize hold timing option to All paths to optimize the register-to-register hold
time paths.
Turn on Enable multicorner timing analysis option for the TimeQuest Timing Analyzer to
analyze the design and generate slack reports for the slow and fast corners.
Use the
Use the
I/O interface uncertainties.
Use the
or applied constraints.
Review the Quartus II messages for any potential problem to your design. Use the
Quartus II Help to understand the messages.
Use parallel processing or incremental compilation in the Quartus II software to reduce
compilation time.
INIT_DONE
set_multicycle_path
derive_pll_clocks
derive_clock_uncertainty
check_timing
pin to show the completion of the initialization process after
constraint to generate a report on any problem with the design
constraint to create generated clocks for PLLs.
command for multicycle path timing analysis.
constraint to apply inter-clock, intra-clock, and
SU
, t
H
, t
CO
, t
PD
, or f
© November 2008 Altera Corporation
MAX
violation.
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