EP2S15F484I4 Altera, EP2S15F484I4 Datasheet - Page 10
EP2S15F484I4
Manufacturer Part Number
EP2S15F484I4
Description
IC STRATIX II FPGA 15K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S15F484I4
Number Of Logic Elements/cells
15600
Number Of Labs/clbs
780
Total Ram Bits
419328
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1877
EP2S15F484I4
EP2S15F484I4
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S15F484I4
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2S15F484I4N
Manufacturer:
ALTERA
Quantity:
210
Company:
Part Number:
EP2S15F484I4N
Manufacturer:
ALTERA
Quantity:
218
Functional Description
Figure 2–1. Stratix II Block Diagram
2–2
Stratix II Device Handbook, Volume 1
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
Each Stratix II device I/O pin is fed by an I/O element (IOE) located at
the end of LAB rows and columns around the periphery of the device.
I/O pins support numerous single-ended and differential I/O standards.
Each IOE contains a bidirectional I/O buffer and six registers for
registering input, output, and output-enable signals. When used with
dedicated clocks, these registers provide exceptional performance and
interface support with external memory devices such as DDR and DDR2
SDRAM, RLDRAM II, and QDR II SRAM devices. High-speed serial
interface channels with dynamic phase alignment (DPA) support data
transfer at up to 1 Gbps using LVDS or HyperTransport
standards.
Figure 2–1
DSP
Block
DSP Blocks for
Multiplication and Full
Implementation of FIR Filters
shows an overview of the Stratix II device.
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
M4K RAM Blocks
for True Dual-Port
Memory & Other Embedded
Memory Functions
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs Support DDR, PCI, PCI-X,
SSTL-3, SSTL-2, HSTL-1, HSTL-2,
LVDS, HyperTransport & other
I/O Standards
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
M-RAM Block
TM
Altera Corporation
LABs
LABs
LABs
LABs
technology I/O
LABs
LABs
LABs
LABs
May 2007